Sharp QT-CD250 (serv.man6) Service Manual ▷ View online
QT-CD250H/W
– 25 –
IC51 VHiLC72121/-1: Electronic Tuning (LC72121) (2/2)
15
Local oscillation, Signal input
AMIN
Input
Serial data input: AMIN is selected when DVS = 0 is set.
When serial data input SNS = 1 is set:
Input frequency is 2-40 MHz.
Signal is sent to the swallow counter directly.
Dividing number to be set is 272- 65535. The actual dividing number
is the same as the setting value.
When serial data input SNS = 0 is set.
Input frequency is 0.5-10 MHz.
Signal is transferred to the 12-bit programmable divider directly.
Dividing number to be set is 4-4095. The actual dividing number is
the same as the setting value.
When serial data input SNS = 1 is set:
Input frequency is 2-40 MHz.
Signal is sent to the swallow counter directly.
Dividing number to be set is 272- 65535. The actual dividing number
is the same as the setting value.
When serial data input SNS = 0 is set.
Input frequency is 0.5-10 MHz.
Signal is transferred to the 12-bit programmable divider directly.
Dividing number to be set is 4-4095. The actual dividing number is
the same as the setting value.
16
Local oscillation, Signal input
FMIN
Input
Serial data input: FMIN is selected when DVS = 1 is set.
Input frequency is 10-160 MHz.
Signal is transferred to the swallow counter through the built-in
prescaler (1/2).
Dividing number to be set is 272-65535. The actual dividing number
is twice as the setting value because there is a built-in prescaler(1/2).
Input frequency is 10-160 MHz.
Signal is transferred to the swallow counter through the built-in
prescaler (1/2).
Dividing number to be set is 272-65535. The actual dividing number
is twice as the setting value because there is a built-in prescaler(1/2).
17
Power supply
VDD
—
Power supply terminal for LC72121 (VDD = 2.7-3.5 V).
Power on reset circuit works when POWER ON.
Power on reset circuit works when POWER ON.
18
Charge pump output
PD
Output
Charge pump output terminal for PLL.
When the local oscillation signal frequency divided by N is higher
then the refernce frequency, "H" level is sent from the PD terminal.
When it is lower, "L" level is sent. When the frequencies are the
same, they become high impedance.
When the local oscillation signal frequency divided by N is higher
then the refernce frequency, "H" level is sent from the PD terminal.
When it is lower, "L" level is sent. When the frequencies are the
same, they become high impedance.
19
L.P.F. Amplifier transistor
AIN
Input
L.P.F. Amplifier transistor
20
L.P.F. Amplifier transistor
AOUT
Output
L.P.F. Amplifier transistor
21
Ground
VSSA
—
Ground terminal for the low-pass filter MOS transistor of LC72121.
22
Xtal
XOUT
Output
Crystal oscillator connection.(4.5 MHz/7.2 MHz)
Port Name
Terminal
Name
Pin No.
Input/Output
Function
Figure 25 BLOCK DIAGRAM OF IC
2
3
4
5
1
7
8
9
6
12
13
14
15
11
17
18
19
10
16
22
21
20
REFERENCE
DIVIDER
PHASE DETECTOR
CHARCE PUMP
UNLOCK
DETECTOR
UNIVERSAL
COUNTER
DATA SHIFT REGISTER
LATCH
12bits PROGRAMMABLE
DIVIDER
SWALLOW COUNTER
1/16, 1/17 4bits
1/2
CCB
I/F
POWER
ON
RESET
PD
AIN
AOUT
VSSa
IFIN
BO1 BO2 BO3 BO4
IO1
IO2
AMIN
FMIN
CE
DI
CL
DO
V
DD
VSSd
XOUT
XIN
VSSx
QT-CD250H/W
– 26 –
IC1 VHiTA2104BN-1: FM /AM IF MPX. (TA2104BN)
Figure 26 BLOCK DIAGRAM OF IC
IC202 VHiTC9260P/-1: Electronic Volume (TC9260P)
2
3
4
5
1
7
8
9
6
12
13
14
15
11
17
18
19
10
16
22
23
24
21
20
FMRE
AM
MIX
FM
MIX
BUFF
BUFF
FM
OSC
AM
OSC
LEVEL
DET
ST
FW
IF
REQ
1/8
AN
DET
AF
BUFF
AF
FM
DET
AGC
FMIF
AMIF
MUTE
ST/MO
FM/AM
FM/AM
VCC
DIYIDE
DECODE
LPF2
LPF1
DET OUT
IFREQ
ST IND
OSC OUT
AM OSC
FM OSC
AM RF IN
FM RF
FM RF OUT
RF GND
MIX OUT
FM RF ON
AM
LOW OUT
IF
BUFF
Vcc
AM IF IN
FM IF IN
GND
AGC
QUAD
R-OUT
L-OUT
MPX IN
2
3
4
5
1
7
8
9
6
12
13
14
15
11
10
16
DATA DECODER, STB GENERATOR
SHIFT REGRATER (13bit)
L-ch
LATCH
R-ch
LATCH
Vss
V
DD
OUT
IN
LD1
LD2
A-GND
CS
CK
L-ch
VOLUME
VOLUME
OUT
IN
LD1
LD2
A-GND
STB
DATA
R-ch
VOLUME
VOLUME
QT-CD250H/W
– 27 –
IC802 VHiTC9457F2-1: Servo/Signal Control (TC9457F2) (1/4)
1*
(OT5)S1
SEG1
Output
Segment signal output to the LCD panel.
2
(OT6)S2
SEG2
Output
Up to 72 segments in a matrix with COM1 to COM4 can be displayed.
3
(OT7)S3
SEG3
Output
All of the S1 to S18 pins can be switched for output ports by a program.
4
(OT8)S4
SEG4
Output
Also, the S15 to S18 pins each can be switched for I/O ports individually.
5
(OT9)S5
SEG5
Output
When set for I/O ports, these pins become Nch open-drain output.
6*
(OT10)S6
SEG6
Output
Furthermore, the S11 to S14 and the P8-0 to P8-3 pins can be switched for
7*
(OT11)S7
SEG7
Output
use as CD signal (CLCK to IPF) input/output pins by a program.
8*
(OT12)S8
SEG8
Output
• CLCK: Subcodes P thru W data readout clock input/output.
9*
(OT13)S9
SEG9
Output
Selected between input and output by a command.
10*
(OT14)S10
SEG10
Output
• DATA: Subcodes P thru W data output.
11*
(CLCK/OT15)
SEG11
Output
• SFSY: Playback system frame sync signal output.
S11
• LRCK: Channel clock (44.1kHz) output.
12*
(DATA/OT16)
SEG12
Output
It outputs a low for L channel and a high for R channel.
S12
Polarity can be inverted by a command.
13*
(SFSY/OT17)
SEG13
Output
• BCK : Bit clock (1.4122MHz) output.
S13
• AOUT: Audio data output.
14*
(LRCK/OT18)
SEG14
Output
• MBOV: Buffer memory-over signal output.
S14
It outputs a high when buffer overflows.
15
(BCK/S15)
SEG15
Output
• IPF : Correction flag output. When AOUT is C2 correction output, it
P8-0
outputs a high indicating that correction is impossible.
16
(AOUT/S16)
SEG16
Output
P8-1
17
(MBOV/S17)
NC
Output
P8-2
18
(IPF/S18)
NC
Output
P8-3
19
MVDD
MVDD1
Input/Output
Power supply pins.
20
MVSS
MVSS1
Input/Output
Normally, apply a voltage of 4.5 to 5.5V to VDD.
In a backup state (when the CKSTP instruction executed), the device's
current consumption is reduced to 1
In a backup state (when the CKSTP instruction executed), the device's
current consumption is reduced to 1
µ
A or less, allowing for the supply
voltage to be lowered to 2.0V.
The device is reset and the program starts from address 0 when a voltage
of 2.7V or more is applied to this pin when it is at 0V (power-on reset).
The device is reset and the program starts from address 0 when a voltage
of 2.7V or more is applied to this pin when it is at 0V (power-on reset).
21*
(K0)P1-0
CD-FUNC
Input
4-bit CMOS I/O ports.
22*
(K1)P1-1
TUNER-FUNC
Input
These ports can be set for input or output bit for bit by a program.
23
(K2)P1-2
DOOR IN
Input
These pins can be pulled up to VDD or down to GND by program.
24
(K3)P1-3
PU IN
Input
Therefore, they can be used as key input pins. Also, when they are set for
I/O port, a change of state in this input can be used to clear the clock stop
or wait mode.
I/O port, a change of state in this input can be used to clear the clock stop
or wait mode.
25
(DCREF)P3-0
CD POWER
Output
5-bit CMOS I/O ports.
26
(ADin1)P3-1
KEY 1
Input
These ports can be set for input or output bit for bit by a program.
27
(ADin2)P3-2
KEY 2
Input
The P3-0 to P4-0 pins serve dual purposes as analog inputs for the internal
28
(ADin3)P3-3
ADIN 3
Input
6-bit 4-channel A/D converters.
29
(BUZR/
NC
Input
The internal A/D converters can complete conversion in 6 instruction cycles
ADin4)P4-0
using a successive approximation method. The required pins can be set for
A/D analog input bit for bit by a program. P3-0 can be set for reference
voltage input, and the internal power supply (MVDD) can be used for this
reference voltage.
The P4-0 pin serves dual purposes as a buzzer output pin.
The buzzer output can be selected from 8 frequencies, 0.625 to 3kHz.
Each selected frequency can be output in one of four modes: continuous,
single, 10Hz intermittent, and 10Hz intermittent at 1Hz interval.
Whether or not to use and how to control the A/D converter and buzzer all
can be set by a prograam.
A/D analog input bit for bit by a program. P3-0 can be set for reference
voltage input, and the internal power supply (MVDD) can be used for this
reference voltage.
The P4-0 pin serves dual purposes as a buzzer output pin.
The buzzer output can be selected from 8 frequencies, 0.625 to 3kHz.
Each selected frequency can be output in one of four modes: continuous,
single, 10Hz intermittent, and 10Hz intermittent at 1Hz interval.
Whether or not to use and how to control the A/D converter and buzzer all
can be set by a prograam.
Port Name
Terminal Name
Pin No.
Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Function
QT-CD250H/W
– 28 –
IC802 VHiTC9457F2-1: Servo/Signal Control (TC9457F2) (2/4)
30
(S12)P4-1
DI
Input
3-bit CMOS I/O ports.
31*
(SO/S11/
DO
Output
DI: Tuner Data Input pin.
SDA)P4-2
DO: Tuner Data Output pin.
32*
(SCK/SCL)
CL
Output
CL: Tuner/Volume Clock Output pin.
P4-3
These ports can be set for input or output bit for bit by a program.
These pins serve dual purposes as input or output pins for the serial
interface circuit (SIO).
The SIO is a 2-wire/3-wire compatible serial interface. 4 or 8 bits of serial
data, beginning with the MSB or LSB, are serially output from the SO/SDA,
pin at each clock edge on the SCK/SCL pin, and the data on S11 or S12
pin is serially input to the device.
The serial clock (SCK/SCL) allows selection between the internal (450/225/
150/75 kHz) and external sources and a selection of the active edge, rise or
fall. Moreover, since the clock and data can be output via Nch open-drain
outputs, variouts, device controls and communication between controllers
can be greatly facilitated.
When an SIO interrupt is enabled, an interrupt is generated at completion
of SIO execution and the program jumps to address 4.
All inputs to SIO contain a Schmitt trigger circuit.
These pins serve dual purposes as input or output pins for the serial
interface circuit (SIO).
The SIO is a 2-wire/3-wire compatible serial interface. 4 or 8 bits of serial
data, beginning with the MSB or LSB, are serially output from the SO/SDA,
pin at each clock edge on the SCK/SCL pin, and the data on S11 or S12
pin is serially input to the device.
The serial clock (SCK/SCL) allows selection between the internal (450/225/
150/75 kHz) and external sources and a selection of the active edge, rise or
fall. Moreover, since the clock and data can be output via Nch open-drain
outputs, variouts, device controls and communication between controllers
can be greatly facilitated.
When an SIO interrupt is enabled, an interrupt is generated at completion
of SIO execution and the program jumps to address 4.
All inputs to SIO contain a Schmitt trigger circuit.
33
TEST0
TEST0
Input
Test mode control input pins.
34
TEST1
TEST1
Input
The test mode is selected when these pins are set high and normal
35
TEST2
TEST2
Input
operation is selected when they are low.
36
TEST3
TEST3
Input
37
TEST4
TEST4
Input
38
TEST5
TEST5
Input
39*
(OT19)/HSO
CE_(PLL)
Output
CE_(PLL): Tuner Chip Enable Input pin.
40*
(OT20)SPCK STB_(VOL)
Output
STB_(VOL): Volume Storobe Input pin.
41*
(OT21)SPDA P_MUTE
Output
P_MUTE: MUTE ON/OFF Output pin.
42*
(OT22)COFS X-BASS
Output
X-BASS: X-BASS ON/OFF Output pin.
43*
DOUT
NC
Input/Output
Digital output pin.
44*
SBSY
NC
Input/Output
Subcode block sync output pin. It outputs a high at the S1 position when
subcode sync is detected.
subcode sync is detected.
45*
SBOK
NC
Input/Output
Subcode Q data CRCC determination result output pin. It outputs a high
when CRCC check is found OK.
when CRCC check is found OK.
46
VDD
VDD1
Input/Output
CD unit's digital block power supply pins.
47
VSS
VSS1
Input/Output
Normally, apply 5V to VDD.
When not using a CD (CD off), this power supply can be turned off, with
only the controller power supply kept active, so that the contrller alone is
operating. In this case, the CD off bit must be set to 1. When this bit is set
to 1, pins 11 through 18 and pins 39 through 42 all are changed for output
ports if they have been set for CD control signal input/output pins.
When not using a CD (CD off), this power supply can be turned off, with
only the controller power supply kept active, so that the contrller alone is
operating. In this case, the CD off bit must be set to 1. When this bit is set
to 1, pins 11 through 18 and pins 39 through 42 all are changed for output
ports if they have been set for CD control signal input/output pins.
48
P2VREF
P2VREF
Input/Output
PLL block-2 VREF pin.
49
PDO
PDO
Input/Output
This pin outputs a phase error between EFM and PLCK signals.
50
TMAX
TMAX
Input/Output
TMAX detection result output pin.
Selected by command bit TMPS.
Longer than preset period: Outputs P2VREF.
Shorter than preset period: Low level (Vss).
Within preset period: High impedance.
Selected by command bit TMPS.
Longer than preset period: Outputs P2VREF.
Shorter than preset period: Low level (Vss).
Within preset period: High impedance.
51
LPFN
LPFN
Input/Output
Inverted input of low-pass filter amp.
52
LPFO
LPFO
Input/Output
Output of low-pass filter amp.
53
PVREF
PVREF
Input/Output
PLL block VREF pin.
54
VCOF
VCOF
Input/Output
VCO filter pin.
55
AVSS
AVSS
Input/Output
Analog block ground pin.
56
SLCO
SLCO
Input/Output
DAC output pin for data slice level generation.
57
RFI
RFI
Input/Output
RF signal input pin.
58
AVDD
AVDD
Input/Output
Analog block power supply pin.
59
RFCT
RFCT
Input/Output
RFRP signal center level input pin.
60
RFZI
RFZI
Input/Output
RFRP zero-cross input pin.
61
RFRP
RFRP
Input/Output
RF ripple signal input pin.
62
FEI
FEI
Input/Output
Focus error signal input pin.
Port Name
Terminal Name
Pin No.
Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Function
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