Sharp QT-CD210 (serv.man3) Service Manual ▷ View online
QT-CD210H/W
– 21 –
• Sled motor operation failure.
Yes
Yes
Is following sled feed signal output the pin 71 (FMO) of IC802
when FF/REW key is pressed after the CD TEST MODE is
seted?
when FF/REW key is pressed after the CD TEST MODE is
seted?
Is sled feed signal output the pins 10 and 11 of IC803?
Is sled feed voltage applied between both terminals of sled
motor?
motor?
No
Check the peripheral parts of IC803. If OK, IC803 is faulty.
No
IC802 is faulty.
Check the BI803/CNS803.
No
Yes
Check the CD mechanism (periphery of sled motor).
If the sled motor does not run when DC2.0V is applied to
both terminals of sled motor, the sled motor is faulty.
If the sled motor does not run when DC2.0V is applied to
both terminals of sled motor, the sled motor is faulty.
• Sled servo failure.
Yes
Is following sled signal output the pin 71 (FMO) of IC802
during playback?
during playback?
Normal.
No
IC802 is faulty.
• Track search failure
Does the sled motor run in FF/REW state when the CD
TEST MODE is set?
TEST MODE is set?
Is the following wave output to the pin 67 (TRO) of IC802
during track search in normal playback?
during track search in normal playback?
Is the following wave output to the pins 12 (TEO) of IC801
during track search in normal playback?
during track search in normal playback?
Yes
Yes
No
Check as stated in item "SLED MOTOR OPERATION FAILURE".
No
IC802 failure.
No
Check the PWB pattern between pin 67 (TRO) of IC802 and pin
28 of IC803.
Check the PWB pattern between pins 25 and 26 of IC803 and
Optical pickup.
If OK. Optical pickup failure.
28 of IC803.
Check the PWB pattern between pins 25 and 26 of IC803 and
Optical pickup.
If OK. Optical pickup failure.
Yes
Is the above wave output to the pins 64 (TEI) and 65 (TEZI)
of IC802 during track serch in normal playback?
of IC802 during track serch in normal playback?
No
Check the PWB pattern between pin 12 (TEO) of IC801 and pins 64
(TEI) and 65 (TEZI) of IC802. If OK. IC801 failure.
(TEI) and 65 (TEZI) of IC802. If OK. IC801 failure.
Normal.
Yes
Yes
Is following sled feed signal input the pins 12 and 13 of IC803
when FF/REW key is pressed after the CD TEST MODE is
seted?
when FF/REW key is pressed after the CD TEST MODE is
seted?
Check the PWB pattern between pin 71 of IC802 and pins 12 and
13 of IC803.
13 of IC803.
No
Is the following wave output to the pin 60 (RFZI) and 61
(RFRP) of IC802 during track search in normal playback?
(RFRP) of IC802 during track search in normal playback?
No
Check the PWB pattern between pin 22 (RFO) and 18 (RFIS), 17
(RFRP) of IC801 and pins 60 and 61 of IC802. If OK. IC801 failure.
(RFRP) of IC801 and pins 60 and 61 of IC802. If OK. IC801 failure.
Yes
TRO
TEO
TEI
TEZI
FF
REW
FMO
FMO
RFRP
RFZI
FF
REW
SL
±
QT-CD210H/W
– 22 –
IC802 VHiTC9457F0-1: Servo/Signal Control (TC9457F0) (1/4)
1*
(OT5)S1
SEG1
Output
Segment signal output to the LCD panel.
2
(OT6)S2
SEG2
Output
Up to 72 segments in a matrix with COM1 to COM4 can be displayed.
3
(OT7)S3
SEG3
Output
All of the S1 to S18 pins can be switched for output ports by a program.
4
(OT8)S4
SEG4
Output
Also, the S15 to S18 pins each can be switched for I/O ports individually.
5
(OT9)S5
SEG5
Output
When set for I/O ports, these pins become Nch open-drain output.
6*
(OT10)S6
SEG6
Output
Furthermore, the S11 to S14 and the P8-0 to P8-3 pins can be switched for
7*
(OT11)S7
SEG7
Output
use as CD signal (CLCK to IPF) input/output pins by a program.
8*
(OT12)S8
SEG8
Output
• CLCK: Subcodes P thru W data readout clock input/output.
9*
(OT13)S9
SEG9
Output
Selected between input and output by a command.
10*
(OT14)S10
SEG10
Output
• DATA: Subcodes P thru W data output.
11*
(CLCK/OT15)
SEG11
Output
• SFSY: Playback system frame sync signal output.
S11
• LRCK: Channel clock (44.1kHz) output.
12*
(DATA/OT16)
SEG12
Output
It outputs a low for L channel and a high for R channel.
S12
Polarity can be inverted by a command.
13*
(SFSY/OT17)
SEG13
Output
• BCK : Bit clock (1.4122MHz) output.
S13
• AOUT: Audio data output.
14*
(LRCK/OT18)
SEG14
Output
• MBOV: Buffer memory-over signal output.
S14
It outputs a high when buffer overflows.
15
(BCK/S15)
CDSEL0
Output
• IPF : Correction flag output. When AOUT is C2 correction output, it
P8-0
outputs a high indicating that correction is impossible.
16
(AOUT/S16)
CDSEL1
Output
P8-1
17
(MBOV/S17)
DOOR IN
Output
P8-2
18
(IPF/S18)
DOOR OUT
Output
P8-3
19
MVDD
MVDD1
—
Power supply pins.
20
MVSS
MVSS1
—
Normally, apply a voltage of 4.5 to 5.5V to VDD.
In a backup state (when the CKSTP instruction executed), the device's
current consumption is reduced to 1
In a backup state (when the CKSTP instruction executed), the device's
current consumption is reduced to 1
µ
A or less, allowing for the supply
voltage to be lowered to 2.0V.
The device is reset and the program starts from address 0 when a voltage
of 2.7V or more is applied to this pin when it is at 0V (power-on reset).
The device is reset and the program starts from address 0 when a voltage
of 2.7V or more is applied to this pin when it is at 0V (power-on reset).
21*
(K0)P1-0
TRAY CLOSE
Input
4-bit CMOS I/O ports.
22*
(K1)P1-1
TRAY OPEN
Input
These ports can be set for input or output bit for bit by a program.
23
(K2)P1-2
PUSEL0
Input
These pins can be pulled up to VDD or down to GND by program.
24
(K3)P1-3
PUSEL1
Input
Therefore, they can be used as key input pins. Also, when they are set for
I/O port, a change of state in this input can be used to clear the clock stop
or wait mode.
I/O port, a change of state in this input can be used to clear the clock stop
or wait mode.
25
(DCREF)P3-0
DISPLAY
Input
5-bit CMOS I/O ports.
26
(ADin1)P3-1
ADIN1
Input
These ports can be set for input or output bit for bit by a program.
27
(ADin2)P3-2
ADIN2
Input
The P3-0 to P4-0 pins serve dual purposes as analog inputs for the internal
28
(ADin3)P3-3
MUTE
Input
6-bit 4-channel A/D converters.
29
(BUZR/
PU IN
Input
The internal A/D converters can complete conversion in 6 instruction cycles
ADin4)P4-0
using a successive approximation method. The required pins can be set for
A/D analog input bit for bit by a program. P3-0 can be set for reference
voltage input, and the internal power supply (MVDD) can be used for this
reference voltage.
The P4-0 pin serves dual purposes as a buzzer output pin.
The buzzer output can be selected from 8 frequencies, 0.625 to 3kHz.
Each selected frequency can be output in one of four modes: continuous,
single, 10Hz intermittent, and 10Hz intermittent at 1Hz interval.
Whether or not to use and how to control the A/D converter and buzzer all
can be set by a prograam.
A/D analog input bit for bit by a program. P3-0 can be set for reference
voltage input, and the internal power supply (MVDD) can be used for this
reference voltage.
The P4-0 pin serves dual purposes as a buzzer output pin.
The buzzer output can be selected from 8 frequencies, 0.625 to 3kHz.
Each selected frequency can be output in one of four modes: continuous,
single, 10Hz intermittent, and 10Hz intermittent at 1Hz interval.
Whether or not to use and how to control the A/D converter and buzzer all
can be set by a prograam.
Port Name
Terminal Name
Pin No.
Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Function
FUNCTION TABLE OF IC
QT-CD210H/W
– 23 –
IC802 VHiTC9457F0-1: Servo/Signal Control (TC9457F0) (2/4)
30
(S12)P4-1
PUSEL2
Input
3-bit CMOS I/O ports.
31*
(SO/S11/
NC
Input/Output
These ports can be set for input or output bit for bit by a program.
SDA)P4-2
These pins serve dual purposes as input or output pins for the serial
32*
(SCK/SCL)
NC
Input/Output
interface circuit (SIO).
P4-3
The SIO is a 2-wire/3-wire compatible serial interface. 4 or 8 bits of serial
data, beginning with the MSB or LSB, are serially output from the SO/SDA,
pin at each clock edge on the SCK/SCL pin, and the data on S11 or S12
pin is serially input to the device.
The serial clock (SCK/SCL) allows selection between the internal (450/225/
150/75 kHz) and external sources and a selection of the active edge, rise or
fall. Moreover, since the clock and data can be output via Nch open-drain
outputs, variouts, device controls and communication between controllers
can be greatly facilitated.
When an SIO interrupt is enabled, an interrupt is generated at completion
of SIO execution and the program jumps to address 4.
All inputs to SIO contain a Schmitt trigger circuit.
data, beginning with the MSB or LSB, are serially output from the SO/SDA,
pin at each clock edge on the SCK/SCL pin, and the data on S11 or S12
pin is serially input to the device.
The serial clock (SCK/SCL) allows selection between the internal (450/225/
150/75 kHz) and external sources and a selection of the active edge, rise or
fall. Moreover, since the clock and data can be output via Nch open-drain
outputs, variouts, device controls and communication between controllers
can be greatly facilitated.
When an SIO interrupt is enabled, an interrupt is generated at completion
of SIO execution and the program jumps to address 4.
All inputs to SIO contain a Schmitt trigger circuit.
33
TEST0
TEST0
Input
Test mode control input pins.
34
TEST1
TEST1
Input
The test mode is selected when these pins are set high and normal
35
TEST2
TEST2
Input
operation is selected when they are low.
36
TEST3
TEST3
Input
37
TEST4
TEST4
Input
38
TEST5
TEST5
Input
39*
(OT19)/HSO
/HSO
Output
CD control output pins.
40*
(OT20)SPCK SPCK
Output
• /HSO: Playback speed mode output.
41*
(OT21)SPDA SPDA
Output
High = normal speed; Low = double speed.
42*
(OT22)COFS COFS
Output
• SPCK: Processor status signal readout clock output (176.4kHz)
• SPDA: Processor status signal output.
• COFS: Correction system frame clock output (7.35kHz)
These pins can be switched for output ports by a program.
• SPDA: Processor status signal output.
• COFS: Correction system frame clock output (7.35kHz)
These pins can be switched for output ports by a program.
43*
DOUT
DOUT
Input/Output
Digital output pin.
44*
SBSY
SBSY
Input/Output
Subcode block sync output pin. It outputs a high at the S1 position when
subcode sync is detected.
subcode sync is detected.
45*
SBOK
SBOK
Input/Output
Subcode Q data CRCC determination result output pin. It outputs a high
when CRCC check is found OK.
when CRCC check is found OK.
46
VDD
VDD1
Input/Output
CD unit's digital block power supply pins.
47
VSS
VSS1
Input/Output
Normally, apply 5V to VDD.
When not using a CD (CD off), this power supply can be turned off, with
only the controller power supply kept active, so that the contrller alone is
operating. In this case, the CD off bit must be set to 1. When this bit is set
to 1, pins 11 through 18 and pins 39 through 42 all are changed for output
ports if they have been set for CD control signal input/output pins.
When not using a CD (CD off), this power supply can be turned off, with
only the controller power supply kept active, so that the contrller alone is
operating. In this case, the CD off bit must be set to 1. When this bit is set
to 1, pins 11 through 18 and pins 39 through 42 all are changed for output
ports if they have been set for CD control signal input/output pins.
48
P2VREF
P2VREF
Input/Output
PLL block-2 VREF pin.
49
PDO
PDO
Input/Output
This pin outputs a phase error between EFM and PLCK signals.
50
TMAX
TMAX
Input/Output
TMAX detection result output pin.
Selected by command bit TMPS.
Longer than preset period: Outputs P2VREF.
Shorter than preset period: Low level (Vss).
Within preset period: High impedance.
Selected by command bit TMPS.
Longer than preset period: Outputs P2VREF.
Shorter than preset period: Low level (Vss).
Within preset period: High impedance.
51
LPFN
LPFN
Input/Output
Inverted input of low-pass filter amp.
52
LPFO
LPFO
Input/Output
Output of low-pass filter amp.
53
PVREF
PVREF
Input/Output
PLL block VREF pin.
54
VCOF
VCOF
Input/Output
VCO filter pin.
55
AVSS
AVSS
Input/Output
Analog block ground pin.
56
SLCO
SLCO
Input/Output
DAC output pin for data slice level generation.
57
RFI
RFI
Input/Output
RF signal input pin.
58
AVDD
AVDD
Input/Output
Analog block power supply pin.
59
RFCT
RFCT
Input/Output
RFRP signal center level input pin.
60
RFZI
RFZI
Input/Output
RFRP zero-cross input pin.
61
RFRP
RFRP
Input/Output
RF ripple signal input pin.
62
FEI
FEI
Input/Output
Focus error signal input pin.
Port Name
Terminal Name
Pin No.
Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Function
QT-CD210H/W
– 24 –
IC802 VHiTC9457F0-1: Servo/Signal Control (TC9457F0) (3/4)
63
SBAD
SBAD
Input/Output
Subbeam add signal input pin.
64
TEI
TEI
Input/Output
Tracking error input pin.
This input is read when tracking servo is on.
This input is read when tracking servo is on.
65
TEZI
TEZI
Input/Output
Tracking error zero-cross input pin.
66
FOO
FOO
Input/Output
Focus equalizer output pin.
67
TRO
TRO
Input/Output
Tracking equalizer output pin.
68
VREF
VREF
Input/Output
Analog reference power supply pin.
69
RFGC
RFGC
Input/Output
RF amplitude adjusting control signal output pin. It outputs 3-level PWM
signals. (PWM carrier = 88.2kHz)
signals. (PWM carrier = 88.2kHz)
70
TEBC
TEBC
Input/Output
Tracking balance control signal output pin. It outputs 3-level PWM signals.
(PWM carrier = 88.2kHz)
(PWM carrier = 88.2kHz)
71
FMO
FMO
Input/Output
Focus equalizer output pin. It outputs 3-level PWM signals.
(PWM carrier = 88.2kHz)
(PWM carrier = 88.2kHz)
72
DMO
DMO
Input/Output
Disc equalizer output pin. It outputs 3-level PWM signals.
(PWM carrier = DSP block 88.2kHz, synchronized to PXO)
(PWM carrier = DSP block 88.2kHz, synchronized to PXO)
73
2VREF
2VREF
Input/Output
Analog reference power supply pin. (2 x VREF)
74
SEL
SEL
Input/Output
APC circuit on/off signal output pin.
When laser is on, this pin goes to a high-impedance state when UHS = low
and outputs a high when UHS = high
When laser is on, this pin goes to a high-impedance state when UHS = low
and outputs a high when UHS = high
75
VDD
VDD2
Input/Output
CD unit's digital block power supply pins.
76
VDD
VSS2
Input/Output
Normally, apply 5V to VDD.
When not using a CD (CD off), this power supply can be turned off, with
only the controller power supply kept active, so that the contrller alone is
operating. In this case, the CD off bit must be set to 1. When this bit is set
to 1, pins 11 through 18 and pins 39 through 42 all are changed for output
ports if they have been set for CD control signal input/output pins.
When not using a CD (CD off), this power supply can be turned off, with
only the controller power supply kept active, so that the contrller alone is
operating. In this case, the CD off bit must be set to 1. When this bit is set
to 1, pins 11 through 18 and pins 39 through 42 all are changed for output
ports if they have been set for CD control signal input/output pins.
77
XVSS
XVSS
Input/Output
CD's crystal oscillator power supply pins.
Normally, connect these pins to the power supply lines that are used in
common for the VDD and VSS pins.
Normally, connect these pins to the power supply lines that are used in
common for the VDD and VSS pins.
78
XI
XI
Input/Output
CD's crystal oscillator input/output pins.
79
XO
XO
Input/Output
Normally, connect 16.934MHz here. This clock is used as the system clock
for the CD. After a system reset, it also is used as the system clock on the
controller side.
for the CD. After a system reset, it also is used as the system clock on the
controller side.
80
XVDD
XVDD
Input/Output
CD's crystal oscillator input/output pins.
Normally, connect these pins to the power supply lines that are used in
common for the VDD and VSS pins.
Normally, connect these pins to the power supply lines that are used in
common for the VDD and VSS pins.
81
DVSR
DVSR
Input/Output
R-channel D/A converter unit ground pin.
82
RO
RO
Input/Output
R-channel data forward output pin.
83
DVRR
DVRR
Input/Output
R-channel reference voltage pin.
84
DVDD
DVDD
Input/Output
D/A converter unit power supply pin.
85
DVRL
DVRL
Input/Output
L-channel reference voltage pin.
86
LO
LO
Input/Output
L-channel data forward output pin.
87
DVSL
DVSL
Input/Output
L-channel D/A converter unit ground pin.
88
NC
NC
Input/Output
NC pins. Normally, connect these pins to ground or leave them open.
89*
NC/VPP
NC
Input/Output
90
/RST
RESET
Input
Device's system reset signal input pin.
The device remains reset while RESET is held low and when RESET is
released back high, the CD unit becomes operational and the program
starts from address 0. Normally, a system reset is asserted when a voltage
of 2.7V or more is applied to VDD when it is at 0V (power-on reset).
Therefore, this pin must be pulled high when used for this purpose.
The device remains reset while RESET is held low and when RESET is
released back high, the CD unit becomes operational and the program
starts from address 0. Normally, a system reset is asserted when a voltage
of 2.7V or more is applied to VDD when it is at 0V (power-on reset).
Therefore, this pin must be pulled high when used for this purpose.
Port Name
Terminal Name
Pin No.
Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Function
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