Sharp QT-CD180 (serv.man5) Service Manual ▷ View online
QT-CD180H/QT-CD180W
– 27 –
IC802 VHiTC9457F0-1: Servo/Signal Control (TC9457F0) (3/4)
63
SBAD
SBAD
Input/Output
Subbeam add signal input pin.
64
TEI
TEI
Input/Output
Tracking error input pin.
This input is read when tracking servo is on.
This input is read when tracking servo is on.
65
TEZI
TEZI
Input/Output
Tracking error zero-cross input pin.
66
FOO
FOO
Input/Output
Focus equalizer output pin.
67
TRO
TRO
Input/Output
Tracking equalizer output pin.
68
VREF
VREF
Input/Output
Analog reference power supply pin.
69
RFGC
RFGC
Input/Output
RF amplitude adjusting control signal output pin. It outputs 3-level PWM
signals. (PWM carrier = 88.2kHz)
signals. (PWM carrier = 88.2kHz)
70
TEBC
TEBC
Input/Output
Tracking balance control signal output pin. It outputs 3-level PWM signals.
(PWM carrier = 88.2kHz)
(PWM carrier = 88.2kHz)
71
FMO
FMO
Input/Output
Focus equalizer output pin. It outputs 3-level PWM signals.
(PWM carrier = 88.2kHz)
(PWM carrier = 88.2kHz)
72
DMO
DMO
Input/Output
Disc equalizer output pin. It outputs 3-level PWM signals.
(PWM carrier = DSP block 88.2kHz, synchronized to PXO)
(PWM carrier = DSP block 88.2kHz, synchronized to PXO)
73
2VREF
2VREF
Input/Output
Analog reference power supply pin. (2 x VREF)
74
SEL
SEL
Input/Output
APC circuit on/off signal output pin.
When laser is on, this pin goes to a high-impedance state when UHS = low
and outputs a high when UHS = high
When laser is on, this pin goes to a high-impedance state when UHS = low
and outputs a high when UHS = high
75
VDD
VDD2
Input/Output
CD unit's digital block power supply pins.
76
VDD
VSS2
Input/Output
Normally, apply 5V to VDD.
When not using a CD (CD off), this power supply can be turned off, with
only the controller power supply kept active, so that the controller alone is
operating. In this case, the CD off bit must be set to 1. When this bit is set
to 1, pins 11 through 18 and pins 39 through 42 all are changed for output
ports if they have been set for CD control signal input/output pins.
When not using a CD (CD off), this power supply can be turned off, with
only the controller power supply kept active, so that the controller alone is
operating. In this case, the CD off bit must be set to 1. When this bit is set
to 1, pins 11 through 18 and pins 39 through 42 all are changed for output
ports if they have been set for CD control signal input/output pins.
77
XVSS
XVSS
Input/Output
CD's crystal oscillator power supply pins.
Normally, connect these pins to the power supply lines that are used in
common for the VDD and VSS pins.
Normally, connect these pins to the power supply lines that are used in
common for the VDD and VSS pins.
78
XI
XI
Input/Output
CD's crystal oscillator input/output pins.
79
XO
XO
Input/Output
Normally, connect 16.934MHz here. This clock is used as the system clock
for the CD. After a system reset, it also is used as the system clock on the
controller side.
for the CD. After a system reset, it also is used as the system clock on the
controller side.
80
XVDD
XVDD
Input/Output
CD's crystal oscillator input/output pins.
Normally, connect these pins to the power supply lines that are used in
common for the VDD and VSS pins.
Normally, connect these pins to the power supply lines that are used in
common for the VDD and VSS pins.
81
DVSR
DVSR
Input/Output
R-channel D/A converter unit ground pin.
82
RO
RO
Input/Output
R-channel data forward output pin.
83
DVRR
DVRR
Input/Output
R-channel reference voltage pin.
84
DVDD
DVDD
Input/Output
D/A converter unit power supply pin.
85
DVRL
DVRL
Input/Output
L-channel reference voltage pin.
86
LO
LO
Input/Output
L-channel data forward output pin.
87
DVSL
DVSL
Input/Output
L-channel D/A converter unit ground pin.
88
NC
NC
Input/Output
NC pins. Normally, connect these pins to ground or leave them open.
89*
NC/VPP
NC
Input/Output
90
/RST
RESET
Input
Device's system reset signal input pin.
The device remains reset while RESET is held low and when RESET is
released back high, the CD unit becomes operational and the program
starts from address 0. Normally, a system reset is asserted when a voltage
of 2.7V or more is applied to VDD when it is at 0V (power-on reset).
Therefore, this pin must be pulled high when used for this purpose.
The device remains reset while RESET is held low and when RESET is
released back high, the CD unit becomes operational and the program
starts from address 0. Normally, a system reset is asserted when a voltage
of 2.7V or more is applied to VDD when it is at 0V (power-on reset).
Therefore, this pin must be pulled high when used for this purpose.
Port Name
Terminal Name
Pin No.
Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Function
QT-CD180H/QT-CD180W
– 28 –
IC802 VHiTC9457F0-1: Servo/Signal Control (TC9457F0) (4/4)
91
/HOLD
RYNCREC
Input
This pin is used to input a signal that requests or clears the hold mode.
Normally, use this pin for CD mode select signal input or battery detection
signal input.
There are two hold modes: clock stop mode (crystal oscillator turned off)
and a wait mode (CPU stopped). These modes are entered by executing
the CKSTP and WAIT instructions, respectively.
The clock stop mode can be requested by a programmed input: low level
detection on HOLD pin or forced execution, and can be cleared by
detecting a high on the HOLD pin or a change of state in its input signal.
When the CKSTP instruction is executed, the clock generator and the CPU
stop operating and the device is placed in a memory backup state. During
this state, the device's current consumption is reduced to 1
Normally, use this pin for CD mode select signal input or battery detection
signal input.
There are two hold modes: clock stop mode (crystal oscillator turned off)
and a wait mode (CPU stopped). These modes are entered by executing
the CKSTP and WAIT instructions, respectively.
The clock stop mode can be requested by a programmed input: low level
detection on HOLD pin or forced execution, and can be cleared by
detecting a high on the HOLD pin or a change of state in its input signal.
When the CKSTP instruction is executed, the clock generator and the CPU
stop operating and the device is placed in a memory backup state. During
this state, the device's current consumption is reduced to 1
µ
A or less.
At the same time, the display output and CMOS output ports are
automatically set low, and the Nch open-drain outputs are turned off.
The wait mode is executed regardles of the input state on the HOLD pin,
with the device's current consumption reduced.
This mode is cleared by a change of state in the HOLD input.
automatically set low, and the Nch open-drain outputs are turned off.
The wait mode is executed regardles of the input state on the HOLD pin,
with the device's current consumption reduced.
This mode is cleared by a change of state in the HOLD input.
92
INTR
REMO-IN
Input
External interrupt input pin.
When the interrupt facility is enabled and a pulse of 1.11 to 2.22
When the interrupt facility is enabled and a pulse of 1.11 to 2.22
µ
s in
duration is applied to this pin, an interrupt is generated and the program
jumps to address 1. Input logic and the active edge (rise or fall) can be
selected for each interrupt input.
Also, the internal 8-bit time clock can be chosen for this interrupt input, in
which case it is possible to count pulses or generate an interrupt at a given
pulse count (address 3).
jumps to address 1. Input logic and the active edge (rise or fall) can be
selected for each interrupt input.
Also, the internal 8-bit time clock can be chosen for this interrupt input, in
which case it is possible to count pulses or generate an interrupt at a given
pulse count (address 3).
93*
MXO
MXO
Input
Crystal oscillator pins for the controller.
94*
MXI
MXI
Input
95
MVSS
MVSS
Input
Power supply pins.
96
MVDD
MVDD
Input
Normally, apply a voltage of 4.5 to 5.5V to VDD.
In a backup state (when the CKSTP instruction executed), the device's
current consumption is reduced to 1
In a backup state (when the CKSTP instruction executed), the device's
current consumption is reduced to 1
µ
A or less, allowing for the supply
voltage to be lowered to 2.0V.
The device is reset and the program starts from address 0 when a voltage
of 2.7V or more is applied to this pin when it is at 0V (power-on reset).
The device is reset and the program starts from address 0 when a voltage
of 2.7V or more is applied to this pin when it is at 0V (power-on reset).
97
OT1
COM1
Output
Common signal outputs to the LCD panel.
98
OT2
COM2
Output
Up to 72 segments in a matrix with S1 to S18 can be displayed.
99
OT3
COM3
Output
Three voltage levels MVDD, VEE (1/2 MVDD), and GND are output for
100
OT4
COM4
Output
Port Name
Terminal Name
Pin No.
Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Function
QT-CD180H/QT-CD180W
– 28 –
IC802 VHiTC9457F0-1: Servo/Signal Control (TC9457F0) (4/4)
91
/HOLD
RYNCREC
Input
This pin is used to input a signal that requests or clears the hold mode.
Normally, use this pin for CD mode select signal input or battery detection
signal input.
There are two hold modes: clock stop mode (crystal oscillator turned off)
and a wait mode (CPU stopped). These modes are entered by executing
the CKSTP and WAIT instructions, respectively.
The clock stop mode can be requested by a programmed input: low level
detection on HOLD pin or forced execution, and can be cleared by
detecting a high on the HOLD pin or a change of state in its input signal.
When the CKSTP instruction is executed, the clock generator and the CPU
stop operating and the device is placed in a memory backup state. During
this state, the device's current consumption is reduced to 1
Normally, use this pin for CD mode select signal input or battery detection
signal input.
There are two hold modes: clock stop mode (crystal oscillator turned off)
and a wait mode (CPU stopped). These modes are entered by executing
the CKSTP and WAIT instructions, respectively.
The clock stop mode can be requested by a programmed input: low level
detection on HOLD pin or forced execution, and can be cleared by
detecting a high on the HOLD pin or a change of state in its input signal.
When the CKSTP instruction is executed, the clock generator and the CPU
stop operating and the device is placed in a memory backup state. During
this state, the device's current consumption is reduced to 1
µ
A or less.
At the same time, the display output and CMOS output ports are
automatically set low, and the Nch open-drain outputs are turned off.
The wait mode is executed regardles of the input state on the HOLD pin,
with the device's current consumption reduced.
This mode is cleared by a change of state in the HOLD input.
automatically set low, and the Nch open-drain outputs are turned off.
The wait mode is executed regardles of the input state on the HOLD pin,
with the device's current consumption reduced.
This mode is cleared by a change of state in the HOLD input.
92
INTR
REMO-IN
Input
External interrupt input pin.
When the interrupt facility is enabled and a pulse of 1.11 to 2.22
When the interrupt facility is enabled and a pulse of 1.11 to 2.22
µ
s in
duration is applied to this pin, an interrupt is generated and the program
jumps to address 1. Input logic and the active edge (rise or fall) can be
selected for each interrupt input.
Also, the internal 8-bit time clock can be chosen for this interrupt input, in
which case it is possible to count pulses or generate an interrupt at a given
pulse count (address 3).
jumps to address 1. Input logic and the active edge (rise or fall) can be
selected for each interrupt input.
Also, the internal 8-bit time clock can be chosen for this interrupt input, in
which case it is possible to count pulses or generate an interrupt at a given
pulse count (address 3).
93*
MXO
MXO
Input
Crystal oscillator pins for the controller.
94*
MXI
MXI
Input
95
MVSS
MVSS
Input
Power supply pins.
96
MVDD
MVDD
Input
Normally, apply a voltage of 4.5 to 5.5V to VDD.
In a backup state (when the CKSTP instruction executed), the device's
current consumption is reduced to 1
In a backup state (when the CKSTP instruction executed), the device's
current consumption is reduced to 1
µ
A or less, allowing for the supply
voltage to be lowered to 2.0V.
The device is reset and the program starts from address 0 when a voltage
of 2.7V or more is applied to this pin when it is at 0V (power-on reset).
The device is reset and the program starts from address 0 when a voltage
of 2.7V or more is applied to this pin when it is at 0V (power-on reset).
97
OT1
COM1
Output
Common signal outputs to the LCD panel.
98
OT2
COM2
Output
Up to 72 segments in a matrix with S1 to S18 can be displayed.
99
OT3
COM3
Output
Three voltage levels MVDD, VEE (1/2 MVDD), and GND are output for
100
OT4
COM4
Output
Port Name
Terminal Name
Pin No.
Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Function
QT-CD180H/QT-CD180W
– 28 –
IC802 VHiTC9457F0-1: Servo/Signal Control (TC9457F0) (4/4)
91
/HOLD
RYNCREC
Input
This pin is used to input a signal that requests or clears the hold mode.
Normally, use this pin for CD mode select signal input or battery detection
signal input.
There are two hold modes: clock stop mode (crystal oscillator turned off)
and a wait mode (CPU stopped). These modes are entered by executing
the CKSTP and WAIT instructions, respectively.
The clock stop mode can be requested by a programmed input: low level
detection on HOLD pin or forced execution, and can be cleared by
detecting a high on the HOLD pin or a change of state in its input signal.
When the CKSTP instruction is executed, the clock generator and the CPU
stop operating and the device is placed in a memory backup state. During
this state, the device's current consumption is reduced to 1
Normally, use this pin for CD mode select signal input or battery detection
signal input.
There are two hold modes: clock stop mode (crystal oscillator turned off)
and a wait mode (CPU stopped). These modes are entered by executing
the CKSTP and WAIT instructions, respectively.
The clock stop mode can be requested by a programmed input: low level
detection on HOLD pin or forced execution, and can be cleared by
detecting a high on the HOLD pin or a change of state in its input signal.
When the CKSTP instruction is executed, the clock generator and the CPU
stop operating and the device is placed in a memory backup state. During
this state, the device's current consumption is reduced to 1
µ
A or less.
At the same time, the display output and CMOS output ports are
automatically set low, and the Nch open-drain outputs are turned off.
The wait mode is executed regardles of the input state on the HOLD pin,
with the device's current consumption reduced.
This mode is cleared by a change of state in the HOLD input.
automatically set low, and the Nch open-drain outputs are turned off.
The wait mode is executed regardles of the input state on the HOLD pin,
with the device's current consumption reduced.
This mode is cleared by a change of state in the HOLD input.
92
INTR
REMO-IN
Input
External interrupt input pin.
When the interrupt facility is enabled and a pulse of 1.11 to 2.22
When the interrupt facility is enabled and a pulse of 1.11 to 2.22
µ
s in
duration is applied to this pin, an interrupt is generated and the program
jumps to address 1. Input logic and the active edge (rise or fall) can be
selected for each interrupt input.
Also, the internal 8-bit time clock can be chosen for this interrupt input, in
which case it is possible to count pulses or generate an interrupt at a given
pulse count (address 3).
jumps to address 1. Input logic and the active edge (rise or fall) can be
selected for each interrupt input.
Also, the internal 8-bit time clock can be chosen for this interrupt input, in
which case it is possible to count pulses or generate an interrupt at a given
pulse count (address 3).
93*
MXO
MXO
Input
Crystal oscillator pins for the controller.
94*
MXI
MXI
Input
95
MVSS
MVSS
Input
Power supply pins.
96
MVDD
MVDD
Input
Normally, apply a voltage of 4.5 to 5.5V to VDD.
In a backup state (when the CKSTP instruction executed), the device's
current consumption is reduced to 1
In a backup state (when the CKSTP instruction executed), the device's
current consumption is reduced to 1
µ
A or less, allowing for the supply
voltage to be lowered to 2.0V.
The device is reset and the program starts from address 0 when a voltage
of 2.7V or more is applied to this pin when it is at 0V (power-on reset).
The device is reset and the program starts from address 0 when a voltage
of 2.7V or more is applied to this pin when it is at 0V (power-on reset).
97
OT1
COM1
Output
Common signal outputs to the LCD panel.
98
OT2
COM2
Output
Up to 72 segments in a matrix with S1 to S18 can be displayed.
99
OT3
COM3
Output
Three voltage levels MVDD, VEE (1/2 MVDD), and GND are output for
100
OT4
COM4
Output
Port Name
Terminal Name
Pin No.
Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Function
