Sharp HT-SB400H (serv.man3) Service Manual ▷ View online
HT-SB400
7 – 6
IC603 RH-IXA248AW00 : System Microcomputer ( IXA248AW ) ( 2/3 )
PIN
NO.
NAME
INPUT/
OUTPUT
FORM
SOFT
PULL-UP
FUNCTION OUTLINE
PORT_TYPE
30
SRS_WDC
INPUT
CMOS INPUT/
OUTPUT
OFF
SRS_WDC
P1_2/KI2/AN10
31
NO USE
OUTPUT
CMOS INPUT/
OUTPUT
OFF
FIX “L”
P1_1/KI1/AN9
32
XRES
OUTPUT
CMOS INPUT/
OUTPUT
OFF
CYPRESS Reset Port
Reset : "H"
Reset : "H"
P1_0/KI0/AN8
33
SRS_RSTB
OUTPUT
CMOS INPUT/
OUTPUT
OFF
NJR Reset
P3_1/TRB0
34
CYS_WAKEUP
OUTPUT
CMOS INPUT/
OUTPUT
OFF
CYPRESS Wake Up Port
L : Normal ; H : Standby
L : Normal ; H : Standby
P3_0/TRA0
35
POWER (DC RELAY)
OUTPUT
CMOS INPUT/
OUTPUT
OFF
MAIN POWER CONTROL.
H: POWER ON ; L: POWER OFF
H: POWER ON ; L: POWER OFF
P6_5/CLK1
36
NO USE
OUTPUT
CMOS INPUT/
OUTPUT
OFF
FIX " L"
P6_4
37
NO USE
OUTPUT
CMOS INPUT/
OUTPUT
OFF
FIX “L”
P6_3
38
LVL_DETECT
INPUT ANALOG/
DIGITAL
CMOS INPUT/
OUTPUT
OFF
LEVEL DETECT
P0_7/AN0
39
NO USE
-
-
-
Port not connected
NC
40
NO USE
-
-
-
Port not connected
NC
41
AREA
INPUT ANALOG/
DIGITAL
CMOS INPUT/
OUTPUT
OFF
Destination setting
P0_6/AN1
42
NO USE
OUTPUT
CMOS INPUT/
OUTPUT
OFF
FIX " L"
P0_5/AN2
43
SYS_PROTECT
INPUT ANALOG/
DIGITAL
CMOS INPUT/
OUTPUT
OFF
System power abnormal detection
P0_4/AN3
44
VREF
INPUT
INPUT
-
Reference Voltage input port (connect to VCC)
P4_2/VREF
45
NO USE
OUTPUT
CMOS INPUT/
OUTPUT
OFF
FIX “L”
P6_0/TRE0
46
AMP_PWDN
OUTPUT
CMOS INPUT/
OUTPUT
OFF
AMP PWR DOWN > set L
Normal operation > set H
Normal operation > set H
P6_2
47
AMP_RESET
OUTPUT
CMOS INPUT/
OUTPUT
OFF
AMP Reset Set 'L' to reset AMP
Normal operation ' H '
Normal operation ' H '
P6_1
48
AMP_INT
INPUT
CMOS INPUT/
OUTPUT
OFF
AMP Interrupt 1
P0_3/AN4
49
PWM_IN
INPUT
CMOS INPUT/
OUTPUT
OFF
Reser AMP when LVL Detect "H" and PWM_IN is "L"
P0_2/AN5
50
AMP_INT2
INPUT
CMOS INPUT/
OUTPUT
OFF
AMP Fault Interupt 2
P0_1/AN6
51
SW_MUTE
OUTPUT
CMOS INPUT/
OUTPUT
OFF
Pre-Out Mute Control
" H " = MUTE ON
" H " = MUTE ON
P0_0/AN7
52
NO USE
OUTPUT
CMOS INPUT/
OUTPUT
OFF
FIX “L”
P3_7/SS0
HT-SB400
7 – 7
IC603 RH-IXA248AWZZ : System Microcomputer ( IXA248AW ) ( 3/3 )
Figure 7-5 BLOCK DIAGRAM OF IC
NO
US
E
SW
_
M
U
T
E
AM
P_
IN
T
2
PW
M
_
IN
AM
P_
IN
T
AM
P_
R
ESET
AM
P_
PW
D
N
NO
US
E
VR
EF
SYS_
PR
OT
EC
T
NO
US
E
AR
EA
NO
US
E
52
51
50
49
48
47
46
45
44
43
42
41
40
P3
_
7
/SS0
P0
_
0
/AN
7
P0
_
1
/AN
6
P0
_
2
/AN
5
P0
_
3
/AN
4
P6
_
1
P6
_
2
P6
_
0
/T
R
E
0
P4
_
2
/VR
E
F
P0
_
4
/AN
3
P0
_
5
/AN
2
P0
_
6
/AN
1
NC
NO USE
1
NC
NC
39
NO USE
SCL
2
P3_5/SCL/SSC
K
K
P0_7/AN0
38
LVL_DETECT
NO USE
3
P3_3/SSI
P6_3
37
NO USE
SDA
4
P3_4/SDA/SCS
P6_4
36
NO USE
MODE
5
MODE
P6_5/CLK1
35
POWER (DC RELAY)
XCIN
6
P4_3/XCIN
P3_0/TRA0
34
CYS_WAKEUP
XCOUT
7
XCOUT
P3_1/TRB0
33
SRS_RSTB
RESET
8
RESET
P1_0/KI0/AN8
32
XRES
XOUT
9
XOUT/P4_7
P1_1/KI1/AN9
31
NO USE
GND
10
VSS/AVSS
P1_2/KI2/AN10
30
SRS_WDC
XIN
11
P4_6/XIN
P6_7/INT3/RXD
29
SYS_STOP
VCC
12
VCC/AVCC
P6_6/INT2/TXD1
28
SRS_MUTE_B
NO USE
13
P2_7/TRDIOD1
27
CYS_INT
P2
_
6
/T
R
D
IOC
1
P2
_
5
/T
R
D
IOB1
P2
_
4
/T
R
D
IOA1
P2
_
3
/T
R
D
IOD
0
P2
_
2
/T
R
D
IOC
0
P2
_
1
/T
R
D
IOB0
P2
_
0
/T
R
D
IOA0
/T
R
DCL
K
P1
_
7
/T
R
A
I0
/IN
T
1
P1
_
6
/C
L
K
0
P1
_
5
/R
XD
0
/(
T
R
A
I0
)
/ (
IN
T
)
P1
_
4
/T
XD
0
P1
_
3
/KI3
/AN
1
1
NC
14
15
16
17
18
19
20
21
22
23
24
25
26
L
E
D_
CL
K
P
W
R_
L
E
D_
S
T
B
Y
2
VF
D
_
BK
L
E
D_
DI
N
LE
D
_
S
T
B
L
E
D_
DO
UT
PW
R
_
L
E
D
_
ST
BY 1
RX
_
IN
VF
D
_
C
L
K
NO
US
E
VF
D
_
SI
VF
D
_
L
A
T
NO
US
E
P4_5/INT0
S
HARP
IXA248A
HT-SB400
7 – 8
IC901 VHISTA333BW-1 : 2.1 Channels High Efficiency Digital Audio System ( STA333BW ) ( 1/2 )
Figure 7-6 BLOCK DIAGRAM OF IC
Figure 7-7 PIN CONFIGURATION OF IC
SA
SCL
SDI
LRCKI
BICKI
RESET
INT LINE
PWDN
XTI
PLL_FILTER
Processor
POWER
SDA
I2C
PLL
EQ, Tone,
Volumes...
Volumes...
Serial Data Input
Channel mapping
Channel mapping
CONTROL
OUT1A
OUT1B
OUT2A
OUT2B
DDX3A
DDX3B
DDX4A/TWARNEXT
DDX4B/EAPD
CONFIG
STATUS
GND_SUB
Vdd_DIG
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
SA
TEST MODE
GND_DIG
SCL
SDA
INT_LINE
RESET
SDI
LRCKI
BICKI
XTI
PLL_GND
PLL_FILTER
PLL_Vdd
POWRDN
GND_DIG
VDD_DIG
TWARN/OUT4B
EAPD/OUT4B
VSS
VCC_REG
OUT2B
OUT2A
OUT1B
GND2
GND1
OUT1A
GND_REG
CONFIG
OUT3B/DDX3B
OUT3A/DDX3A
Vdd
Vcc2
Vcc1
HT-SB400
7 – 9
IC901 VHISTA333BW-1 : 2.1 Channels High Efficiency Digital Audio System ( STA333BW ) ( 2/2 )
PIN
NAME
TYPE
DESCRIPTION
1
GND_SUB
Input / Output
Subtrate ground
2
SA
Input
I²C Select Address
3
Test_Mode
Input
This pin must be connected to GROUND
4
Vss
Input / Output
Internal reference at Vcc - 3.3V
5
Vcc_REG
Input / Output
Internal Vcc reference
6
OUT2B
Output
Output half bridge 2B
7
GND2
Input / Output
Power negative supply
8
Vcc2
Input / Output
Power positive supply
9
OUT2A
Output
Output half bridge 2A
10
OUT1B
Output
Output half bridge 1B
11
Vcc1
Input / Output
Power positive supply
12
GND1
Input / Output
Power negative supply
13
OUT1A
Input / Output
Output half bridge 1A
14
GND_REG
Input / Output
Internal Ground reference
15
Vdd
Input / Output
Internal 3.3V reference voltage
16
CONFIG
Input
Paralleled mode command
17
OUT3B/DDX3B
Output
PWM Out CH3B - External Bridge
18
OUT3A/DDX3A
Output
PWM Out CH3A - External Bridge
19
EAPD/OUT4A
Output
Power Down for External Bridge
20
TWARN/OUT4B
Input
Thermal warning from External Bridge
21
Vdd_DIG
Input / Output
Positive Supply Digital
22
GND_DIG
Input / Output
Digital Ground
23
PWRDN
Input
Power Down
24
PLL_Vdd
Input / Output
Positive Supply for PLL
25
PLL_FILTER
Input
Connection to PLL Filter
26
PLL_GND
Input / Output
Negative Supply for PLL
27
XTI
Input
PLL Input Clock
28
BICKI
Input
I²S Serial Clock
29
LRCKI
Input
I²S Left / Right Clock
30
SDI_12
Input
I²S Serial Data Channels 1&2
31
RESET
Input
Reset
32
INT_LINE
Output
Fault Interrupt
33
SDA
Input / Output
I²C Serial Data
34
SCL
Input
I²C Serial Clock
35
GND_DIG
Input / Output
Digital Ground
36
Vdd_DIG
Input / Output
Digital Supply
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