Sharp HT-SB250 (serv.man2) Service Manual ▷ View online
HT-SB250
7 – 1
CHAPTER 7. OTHERS
[1] Function Table Of IC
IC601 VHIWM8775++-1 : 96kHz ADC with 4 Channel I/P Multiplexer ( WM8775 ) ( 1/2 )
Figure 7-1 BLOCK DIAGRAM OF IC
Figure 7-2 PIN CONFIGURATION OF IC
CONTROL INTERFACE
MCLK
ALC
INPUT MIXER
WM8775
AUDIO INTERFACE
AND
DIGITAL FILTERS
BCLK
ADCLRC
DOUT
DI
CE
CL
MODE
DV
D
D
DGND
AIN4R
VMID
STEREO
ADC
AG
N
D
AV
D
D
ADCREFP
ADCREFGND
VMID
ADC
AIN4L
AIN3R
AIN3L
AIN2R
AIN2L
AIN1R
AIN1L
AINVGR
AINVGL
AINOPR
AINOPL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AIN1L
BCLK
MCLK
DOUT
ADCLRC
DGND
DVDD
MODE
CE
DI
CL
NC
VMIDADC
ADCREFGND
AIN1R
AIN2L
AIN2R
AIN3L
AIN3R
AIN4L
AIN4R
AINOPL
AINVGL
AINOPR
AINVGR
AGND
AVDD
ADCREFP
HT-SB250
7
– 2
IC601 VHIWM8775++-1 : 96kHz ADC with 4 Channel I/P Multiplexer ( WM8775 ) ( 2/2 )
IC Pin Descriptions
PIN
NAME
TYPE
DESCRIPTION
1
AIN1L
Analogue Input
Channel 1 left input multiplexer virtual ground
2
BCLK
Digital Input / Output
ADC audio interface bit clock
3
MCLK
Digital Input
Master ADC clock; 256,384,512 or 768fs (fs = word clock frequency)
4
DOUT
Digital Output
ADC data output
5
ADCLRC
Digital Input / Output
ADC left / right word clock
6
DGND
Supply
Digital negative supply
7
DVDD
Supply
Digital positive supply
8
MODE
Digital Input
Serial Interface Mode select
9
CE
Digital Input
Serial Interface Latch signal
10
DI
Digital Input / Output
Serial Interface data
11
CL
Digital Input
Serial Interface clock
12
NC
NC
No Connection
13
VMIDADC
Analogue Output
ADC midrail divider decoupling pin; 10uF external decoupling
14
ADCREFGND
Supply
ADC negative supply and substrate connection
15
ADCREFP
Analogue Output
ADC positive reference decoupling pin; 10uF external decoupling
16
AVDD
Supply
Analogue positive supply
17
AGND
Supply
Analogue negative supply and substrate connection
18
AINVGR
Analogue Input
Right channel multiplexer virtual ground
19
AINOPR
Analogue Output
Right channel multiplexer output
20
AINVGL
Analogue Input
Left channel multiplexer virtual ground
21
AINOPL
Analogue Output
Left channel multiplexer output
22
AIN4R
Analogue Input
Channel 4 right input multiplexer virtual ground
23
AIN4L
Analogue Input
Channel 4 left input multiplexer virtual ground
24
AIN3R
Analogue Input
Channel 3 right input multiplexer virtual ground
25
AIN3L
Analogue Input
Channel 3 left input multiplexer virtual ground
26
AIN2R
Analogue Input
Channel 2 right input multiplexer virtual ground
27
AIN2L
Analogue Input
Channel 2 left input multiplexer virtual ground
28
AIN1R
Analogue Input
Channel 1 right input multiplexer virtual ground
HT-SB250
7 – 3
IC602 VHINJU260409B : SRS WOW Hardware Data Processor ( NJU26040-09B ) ( 1/2 )
Figure 7-3 BLOCK DIAGRAM OF IC
Figure 7-4 PIN CONFIGURATION OF IC
AD1/SDIN
SERIAL
HOST
INTERFACE
SERIAL AUDIO
INTERFACE
PROGRAM
CONTROL
ALU
DSP ARITHMETIC UNIT
24-BIT x 24-BIT
MULTIPLIER
ADDRESS GENERATION UNIT
TIMING
GENERATOR
DATA
RAM
FIRMWARE
RAM
GPIO
PROC
BCKO
BCKI
LRO
LRI
SDO0
SD10
SDI1
L/R
SW
SDI2
SDO1
MUTEb
SEL
WDC
SCL/SCK
SDA/SDOUT
RESETb
MCK
CLK
CLKOUT
AD2/SSb
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
VSS
TEST0
TEST0
TEST0
TEST1
SDO1
SDO0
LRO
BCKO
MCK
SEL
PROC
MUTEb
NJU26040
SSOP32
WDC
VDD
VSS
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
SDA/SDOUT
SCL/SCK
CLKOUT
SDI2
SDI1
SDI0
LRI
BCKI
CLK
AD1/SDIN
AD2/SSb
RESETb
VDD
VDD
VSS
HT-SB250
7
– 4
IC602 VHINJU260409B : SRS WOW Hardware Data Processor ( NJU26040-09B ) ( 2/2 )
Note: I :
I
: Input
I -
: Input (Pull-down)
O
: Output
OD
: Bi-directional (Open Drain) This pin requires a pull-up resistance.
I / O +
: Bi-directional (with Pull-up resistance).
I / O -
: Bi-directional (with Pull-down resistance).
PIN
NAME
Input / Output
DESCRIPTION
1,7,8,25
VDD
---
Power Supply + 3.3V
2
SDA/SDOUT
OD
I²C Input / Output / 4-Wire Serial Output. This pin rquires a pull-up resistance in
both I²C bus and 4-Wire serial mode.
both I²C bus and 4-Wire serial mode.
3
SCL/SCK
I
I²C clock / Serial clock
4
AD1/SDIN
I
I²C Address / Serial In
5
AD2/SSb
I
I²C Address / Serial Enable
6
RESETb
I
Reset (RESETb = 'Low' : DSP Reset)
9,24,32
VSS
---
GND
10
CLKOUT
O
OSC Output
11
CLK
I
OSC Clock Input
12
SDI2
I
Audio Data Input 2 (L/R)
13
SDI2
I
Audio Data Input 1 (L/R)
14
SDI0
I
Audio Data Input 0 (L/R)
15
LRI
I
LR Clock Input
16
BCKI
I
Bit Clock Input
17
BCKO
O
Bit Clock Output
18
LRO
O
LR Clock Output
19
SDO0
O
Audio Data Output 0 (L/R)
20
SDO1
O
Audio Data Output 1 (SW)
21
TEST1
O
for Test (Non connect)
22
MCK
O
Master Clock Output for A/D, D/A
23,30,31
TEST0
I -
for Test (connected to VSS)
26
WDC
OD
Watchdog clock output (open drain output)
27
MUTEb
I
Master Volume level, After Reset DSP ("1" : 0dB "0" : Mute)
28
PROC
I
After Reset DSP ("1" : Normal "0" : Wait from Command)
29
SEL
I
Select I²C or Serial bus ( '1' : Serial / '0' : I²C - Bus)
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