Sharp HT-DV40H (serv.man4) Service Manual ▷ View online
HT-DV40H
8 – 38
IC11 VHILC750512-1 : AUDIO ENHANCER ( LC750512 ) ( 1/2 )
PIN DESCRIPTION
Pin No.
Terminal Name
Input / Output
Function
1
PLLPWRR
Input
Power ring for PLL (ESD) (+1.8 V).
2
PLLGNDR
—
GND for PLL (ESD).
3
PLLAVDD
Input
Power supply for PLL (+1.8 V).
4
PLLAVSS
—
GND for PLL.
5
PLLDVDD
Input
Digital power supply for PLL (+1.8 V).
6
PLLDVSS
—
Digital GND for PLL (ESD).
7
TEST2
Input
Test terminal.
8
TEST3
Input
Test terminal.
9
DVSS4
—
Digital GND.
10
DVDD4
Input
Digital power supply (+1.8 V).
11
XVSS
—
GND for crystal.
12
XOUT
Output
Crystal oscillating output.
13
XIN
Input
Crystal oscillating input.
14
XVDD
Input
Power supply for crystal (+3.3 V).
15
CVDD4
Input
Digital power supply (+3.3 V).
16
CVSS4
—
Digital GND.
17
TEST0
Input
Test terminal.
18
TEST1
Input
Test terminal.
19
TEST4
Input
Test terminal.
20
TEST5
Input
Test terminal.
21
BVSS1
—
Logic GND in analog chip.
22
BVDD1
Input
Logic power supply in analog chip (+3.3 V).
23
AVSS4
—
DAC analog GND.
24
AVDD4
Input
DAC analog VDD (+5 V).
25
AVDD3
Input
EVR analog VDD (+5 V).
26
AVSS3
—
EVR analog GND.
27
AOUT1
Output
Lch EVR output.
28
EVRINL
Input
Lch EVR input.
29
DAOUTL
Output
Lch DAC analog output.
30
DAOUTR
Output
Rch DAC analog output.
31
EVRINR
Input
Rch EVR input.
32
AOUT2
Output
Rch EVR output.
33
AVSS2
—
GND for VREF.
34
AVDD2
Input
VDD for VREF (+5 V).
35
VREF2
Output
Reference voltage output terminal 2 (DAC, EVR).
36
VREF1
Output
Reference voltage output terminal 1 (ADC).
37
INL
Input
Lch ADC analog input.
38
INR
Input
Rch ADC analog input.
39
AVSS1
—
ADC analog GND.
40
AVDD1
Input
ADC analog power supply (+5V)
41*
TEST6
Input/Output
Test terminal.
42
XSEL0
Input/Output
Crystal frequency setting signal 0.
43
XSEL1
Input/Output
Crystal frequency setting signal 1.
44
XSEL2
Input/Output
Crystal frequency setting signal 2.
45
CVSS1
—
Digital GND.
46
CVDD1
Input
Digital power supply (+3.3 V).
47
LRCKI
Input
LR clock input.
48
BCKI
Input
Bit clock input.
49
DATAI
Input
Data input.
50
SCKII
—
External clock input.
51
DVSS1
—
Digital GND.
52
DVDD1
Input
Digital power supply (+1.8V).
53*
SCKO
Output
DAC master clock output.
54
TEST7
Input
Test terminal.
55*
DATAO2
Output
Data output 2.
56*
DATAO1
Output
Data output 1.
57*
DATAO0
Output
Data output 0.
58*
BCKO
Output
Bit clock output.
59*
LRCKO
Output
LR clock output.
60
CVSS2
—
Digital GND.
61
CVDD2
Input
Digital power supply (+3.3 V).
62
XPDESC
Input
DSP power down release signal (L-Active).
63*
PDEN
Output
DSP power down signal (H-Active).
64
DVSS2
—
Digital GND.
HT-DV40H
8 – 39
IC11 VHILC750512-1 : AUDIO ENHANCER ( LC750512 ) ( 2/2 )
BLOCK DIAGRAM
Figure 8-7 BLOCK DIAGRAM OF IC
65
DVDD2
Input
Digital power supply (+1.8V).
66
PWDB
Input
Power down input (L-Active).
67
RSTB
Input
Reset input (L-Active).
68
INTB
Input
Interrupt input (“H” Fixed input).
69
MCUIFSEL
Input
Microprocessor I/F (CCB: Low; I2C: High). Select input.
70
CE
Input
Microprocessor I/F chip enable.
71
SCL/CL
Input
Microprocessor I/F clock input.
72
I2CBUSY/DI
Input/Output
Microprocessor I/F data input/12CBUSY output (H-Active).
73
SDA/DO
Input/Output
Microprocessor I/F data input/output (Nch open drain).
74
DVSS3
—
Digital GND.
75
DVDD3
Input
Digital power supply (+1.8V).
76
MRREQ
Output
DSP-MCU communication error flag (H-Active).
77*
GPFLAG
Output
DSP-MCU general-purpose flag (H-Active).
78*
EMPF
Output
CCB input register status monitor flag.
79
CVSS3
—
Digital GND.
80
CVDD3
Input
Digital power supply (+3.3 V).
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal Name
Input / Output
Function
38
INR
DAOUTL
DAOUTR
EVRINL
EVRINR
AOUT1
AOUT2
LRCKO
BCKO
DATAO0
DATAO0
DATAO1
DATAO2
PLLAVDD
PLLAVSS
PLLAVSS
PLLDVDD
PLLDVSS
PLLDVSS
AVDD1-4
AVSS1-4
BVDD1
BVSS1
BVSS1
CVSS1-4
CVDD1-4
DVSS1-4
DVDD1-4
XVSS
VREF1
VREF2
VREF2
XVDD
ADC
(20bit)
DSP CORE
24bit
DAC
(20bit)
L.P.F.
Program ROM
Data RAM
Delay RAM
37
INL
LRCKI
BCKI
DATAI
ADC
(20bit)
47
55
3
4
5
6
24,25,34,40
23,26,33,39
15,46,61,80
16,45,79,60
10,52,65,75
9,51,64,74
14
11
36
22
21
48
49
1
2
13
12
78
77
76
70
71
72
73
69
42,43,44
67
66
63
62
68
41
50
53
35
7,817,18,19,20,41
Audio I/F
PLLPWPR
PLLGNDR
XSEL0,1,2
XIN
XOUT
EMPF
GPFLAG
MRREQ
CE
SCL/CL
I2CBUSY/DI
SDA/DO
PWDB
PDEN
XPDESC
INTB
TEST7,5-0
TEST6
SCKI
SCKO
MCUFISEL
RSTB
PLL
VCO
CCB or I
2
C
DAC
(20bit)
Audio I/F
L.P.F.
R
56
57
58
59
32
31
30
Vref
Audio I/F
Audio I/F
R
27
28
29
Vref
HT-DV40H
8 – 40
IC13 VHIAK4683EQ-1 : MULTI CHANNEL AUDIO CODEC ( AK4683 ) ( 1/3 )
BLOCK DIAGRAM
Figure 8-8 BLOCK DIAGRAM OF IC
ADC
Audio
I/F
ADC
LIN1
LIN2
LIN3
LIN4
LIN5
LIN6
LIN2
LIN3
LIN4
LIN5
LIN6
HPF,
DVOL
DAC
DVOL
LPF
LOUT1
ROUT1
LOUT2
ROUT2
HPL
HPR
DAC
DVOL
LPF
DAC
DVOL
LPF
DAC
DVOL
LPF
DAC1
Audio
I/F
4:2
Input
Selector
Clock
Recovery
X’tal
Oscillator
µ
P I/F
XTO
XTI
BICKB
LRCKB
LRCKB
TX
SDTOB
SDOUT
DAIF
Decoder
ADC
DIT
SDTIB
RIN1
RIN2
RIN3
RIN4
RIN5
RIN6
RIN2
RIN3
RIN4
RIN5
RIN6
ROPIN
RISEL
RISEL
I2C
CSN
CCLK
CDTI
CDTO
CCLK
CDTI
CDTO
RX0
RX1
RX2
RX3
RX1
RX2
RX3
LISEL
LOPIN
LOPIN
SDTOB0/1 bit
DIT0/1 bit
DIT bit
MCLK2
SDTOA
OLRCKA
OLRCKA
BICKA
ILRCKA
ILRCKA
SDTIA1
SDTIA2
SDTIA3
SDTIA2
SDTIA3
MCKO
SDTOA0/1 bit
DIR
ADC
SDTIB
SDTIA1
Through
DIT
RMCLK
DAC10/11/12,
DAC20/21/22 bit
IPS0/1, OPS0/1 bit
LIN0/1/2, RIN0/1/2 bit
DIR
ADC
SDTIA1
off
DIR
ADC
SDTIB
off
DAC2
Audio
I/F
DIR
ADC
SDTIB
SDTIA1
SDTIA2
SDTIA3
HPF,
DVOL
DIR
ADC
SDTIB
SDTIA1
SDTIA2
SDTIA3
PORTB
PORTA
HT-DV40H
8 – 41
IC13 VHIAK4683EQ-1 : MULTI CHANNEL AUDIO CODEC ( AK4683 ) ( 2/3 )
PIN CONFIGURATION
PVDD
1
RX0
2
I2C
3
RX1
4
RX2
5
RX3
6
INT
7
VOUT
8
CDTO
9
LRCKB
10
BICKB
11
SDTOB
12
OLRCKA
13
ILRCKA
14
BICKA
15
SDTOA
16
64
R
63
PV
SS
62
RI
N6
61
LI
N6
60
RI
N5
59
LIN
5
58
RI
N4
57
LIN
4
56
RI
N3
55
LI
N3
54
RI
N2
53
LI
N2
52
RI
N1
51
LIN
1
50
AV
DD1
49
17
MC
KO
18
TVD
D
19
DV
S
S
20
DV
DD
21
XTI
22
XT
O
23 24
MC
L
K
2
TX
25
PD
N
26
CDT
I
27
CCL
K
28
CS
N
29
SDTI
A
1
30
SDTI
A
2
31
SDTI
A
3
32
SD
TI
B
RISEL
48
ROPIN
47
LOPIN
46
LISEL
45
AVSS2
44
AVDD2
43
VCOM
42
ROUT2
41
LOUT2
40
ROUT2
39
LOUT2
38
MUTET
37
HPL
36
HPR
35
HVSS
34
HVDD
33
AK4683EQ
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AV
SS1
