Sharp HT-DV40H (serv.man4) Service Manual ▷ View online
HT-DV40H
8 – 36
IC10 VHINJU26220FN : DOLBY VIRTUAL SPEAKER / HEADPHONE DECODER ( NJU26220FN ) ( 2/3 )
PIN CONFIGURATION
Figure 8-6 BLOCK DIAGRAM OF IC
NJU26220
SDO2
SDO1
SDO0
VDDIO
VSSIO
VSS
VDD
SD13
SD12
SD11
SD10
LRI
TEST
TEST
TEST
RESETb
VDDIO
VSSIO
CLK
CLKOUT
VDD
VSS
VSSPLL
VDDPLL
SDO3
LRO
BCKO
MCK
VDDIO
VSSIO
VSS
VDD
SDA/SDOUT
SCL/SCK
AD2/SSb
AD1/SDIN
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
36
35
34
33
32
31
30
29
28
27
26
25
VDDIO
BCKI
VSSIO
VSS
VDD
TEST
MUTEb
WDC
PROC
VSSIO
VDDIO
SEL
1
2
3
4
5
6
7
8
9
10
11
12
HT-DV40H
8 – 37
IC10 VHINJU26220FN : DOLBY VIRTUAL SPEAKER / HEADPHONE DECODER ( NJU26220FN ) ( 3/3 )
PIN DESCRIPTION
Pin No.
Symbol
Input/Output
Function
1,11,20,32,40
VDDIO
-
I/O Power Supply +3.3V
2
BCKI
Input
Bit Clock Input
3,10,19,31,41
VSSIO
-
I/O GND
4,15,30,42
VSS
-
Core GND
5,16,29,43
VDD
-
Core Power Supply +1.8V
6
TEST
Input
for test (connected to VSSIO through 3.3k
Ω resistance.)
7
MUTEb*
Input
Master Volume level, After reset DSP (“1” : 0dB, “0” : Mute)
8
WDC*
OD
Clock for Watch Dog Timer (Open Drain Output)
9
PROC*
Input
After Reset DSP. (“1” : Normal, “0” : Wait from Command)
12
SEL
Input
Select I
2
C or Serial Bus (“1” : Serial, “0” : I
2
C-Bus)
13
VDDPLL
-
PLL Analog Power Supply +1.8V
14
VSSPLL
-
PLL Analog GND
17
CLKOUT
Output
OSC Output
18
CLK
Input
X’tal CLock Input (12.288MHz)
21
RESETb
Input
Reset (RESETb=’0’ : DSP Reset)
22
TEST
Input
for TEST (Connect to VDDIO)
23,24
TEST
Input
for TEST (Connect to VSSIO)
25
AD1/SDIN
Input
I
2
C Address / Serial Input
26
AD2/SSb
Input
I
2
C Address / Serial Enable
27
SCI/SCK
Input
I
2
C Clock / Serial Clock
28
SDA/SDOUT
Input/Output
I
2
C I/O (Open Drain output) / Serial Output (CMOS output)
I
2
C Bus mode : SDA pin requires a pull-up resistance
4-wire Serial mode : SDOUT does not require a pull-up resistance.
33
MCK
Output
Master Clock Output (CLK Terminal=27 pin Buffer Out)
34
BCKO
Output
Bit Clock Output
35
LRO
Output
LR Clock Output
36
SDO3
Output
Audio Data Output 3 (SL/SR)
37
SDO2
Output
Audio Data Output 2 (C/SW)
38
SDO1
Output
Audio Data Output 1 (L/R)
39
SDO0
Output
Audio Data Output 0 (Monitor output)
44
SDI3
Input
Audio Data Input 3
45
SDI2
Input
Audio Data Input 2
46
SDI1
Input
Audio Data Input 1
47
SDI0
Input
Audio Data Input 0
48
LRI
Input
LR Clock Input
HT-DV40H
8 – 38
IC11 VHILC750512-1 : AUDIO ENHANCER ( LC750512 ) ( 1/2 )
PIN DESCRIPTION
Pin No.
Terminal Name
Input / Output
Function
1
PLLPWRR
Input
Power ring for PLL (ESD) (+1.8 V).
2
PLLGNDR
—
GND for PLL (ESD).
3
PLLAVDD
Input
Power supply for PLL (+1.8 V).
4
PLLAVSS
—
GND for PLL.
5
PLLDVDD
Input
Digital power supply for PLL (+1.8 V).
6
PLLDVSS
—
Digital GND for PLL (ESD).
7
TEST2
Input
Test terminal.
8
TEST3
Input
Test terminal.
9
DVSS4
—
Digital GND.
10
DVDD4
Input
Digital power supply (+1.8 V).
11
XVSS
—
GND for crystal.
12
XOUT
Output
Crystal oscillating output.
13
XIN
Input
Crystal oscillating input.
14
XVDD
Input
Power supply for crystal (+3.3 V).
15
CVDD4
Input
Digital power supply (+3.3 V).
16
CVSS4
—
Digital GND.
17
TEST0
Input
Test terminal.
18
TEST1
Input
Test terminal.
19
TEST4
Input
Test terminal.
20
TEST5
Input
Test terminal.
21
BVSS1
—
Logic GND in analog chip.
22
BVDD1
Input
Logic power supply in analog chip (+3.3 V).
23
AVSS4
—
DAC analog GND.
24
AVDD4
Input
DAC analog VDD (+5 V).
25
AVDD3
Input
EVR analog VDD (+5 V).
26
AVSS3
—
EVR analog GND.
27
AOUT1
Output
Lch EVR output.
28
EVRINL
Input
Lch EVR input.
29
DAOUTL
Output
Lch DAC analog output.
30
DAOUTR
Output
Rch DAC analog output.
31
EVRINR
Input
Rch EVR input.
32
AOUT2
Output
Rch EVR output.
33
AVSS2
—
GND for VREF.
34
AVDD2
Input
VDD for VREF (+5 V).
35
VREF2
Output
Reference voltage output terminal 2 (DAC, EVR).
36
VREF1
Output
Reference voltage output terminal 1 (ADC).
37
INL
Input
Lch ADC analog input.
38
INR
Input
Rch ADC analog input.
39
AVSS1
—
ADC analog GND.
40
AVDD1
Input
ADC analog power supply (+5V)
41*
TEST6
Input/Output
Test terminal.
42
XSEL0
Input/Output
Crystal frequency setting signal 0.
43
XSEL1
Input/Output
Crystal frequency setting signal 1.
44
XSEL2
Input/Output
Crystal frequency setting signal 2.
45
CVSS1
—
Digital GND.
46
CVDD1
Input
Digital power supply (+3.3 V).
47
LRCKI
Input
LR clock input.
48
BCKI
Input
Bit clock input.
49
DATAI
Input
Data input.
50
SCKII
—
External clock input.
51
DVSS1
—
Digital GND.
52
DVDD1
Input
Digital power supply (+1.8V).
53*
SCKO
Output
DAC master clock output.
54
TEST7
Input
Test terminal.
55*
DATAO2
Output
Data output 2.
56*
DATAO1
Output
Data output 1.
57*
DATAO0
Output
Data output 0.
58*
BCKO
Output
Bit clock output.
59*
LRCKO
Output
LR clock output.
60
CVSS2
—
Digital GND.
61
CVDD2
Input
Digital power supply (+3.3 V).
62
XPDESC
Input
DSP power down release signal (L-Active).
63*
PDEN
Output
DSP power down signal (H-Active).
64
DVSS2
—
Digital GND.
HT-DV40H
8 – 39
IC11 VHILC750512-1 : AUDIO ENHANCER ( LC750512 ) ( 2/2 )
BLOCK DIAGRAM
Figure 8-7 BLOCK DIAGRAM OF IC
65
DVDD2
Input
Digital power supply (+1.8V).
66
PWDB
Input
Power down input (L-Active).
67
RSTB
Input
Reset input (L-Active).
68
INTB
Input
Interrupt input (“H” Fixed input).
69
MCUIFSEL
Input
Microprocessor I/F (CCB: Low; I2C: High). Select input.
70
CE
Input
Microprocessor I/F chip enable.
71
SCL/CL
Input
Microprocessor I/F clock input.
72
I2CBUSY/DI
Input/Output
Microprocessor I/F data input/12CBUSY output (H-Active).
73
SDA/DO
Input/Output
Microprocessor I/F data input/output (Nch open drain).
74
DVSS3
—
Digital GND.
75
DVDD3
Input
Digital power supply (+1.8V).
76
MRREQ
Output
DSP-MCU communication error flag (H-Active).
77*
GPFLAG
Output
DSP-MCU general-purpose flag (H-Active).
78*
EMPF
Output
CCB input register status monitor flag.
79
CVSS3
—
Digital GND.
80
CVDD3
Input
Digital power supply (+3.3 V).
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal Name
Input / Output
Function
38
INR
DAOUTL
DAOUTR
EVRINL
EVRINR
AOUT1
AOUT2
LRCKO
BCKO
DATAO0
DATAO0
DATAO1
DATAO2
PLLAVDD
PLLAVSS
PLLAVSS
PLLDVDD
PLLDVSS
PLLDVSS
AVDD1-4
AVSS1-4
BVDD1
BVSS1
BVSS1
CVSS1-4
CVDD1-4
DVSS1-4
DVDD1-4
XVSS
VREF1
VREF2
VREF2
XVDD
ADC
(20bit)
DSP CORE
24bit
DAC
(20bit)
L.P.F.
Program ROM
Data RAM
Delay RAM
37
INL
LRCKI
BCKI
DATAI
ADC
(20bit)
47
55
3
4
5
6
24,25,34,40
23,26,33,39
15,46,61,80
16,45,79,60
10,52,65,75
9,51,64,74
14
11
36
22
21
48
49
1
2
13
12
78
77
76
70
71
72
73
69
42,43,44
67
66
63
62
68
41
50
53
35
7,817,18,19,20,41
Audio I/F
PLLPWPR
PLLGNDR
XSEL0,1,2
XIN
XOUT
EMPF
GPFLAG
MRREQ
CE
SCL/CL
I2CBUSY/DI
SDA/DO
PWDB
PDEN
XPDESC
INTB
TEST7,5-0
TEST6
SCKI
SCKO
MCUFISEL
RSTB
PLL
VCO
CCB or I
2
C
DAC
(20bit)
Audio I/F
L.P.F.
R
56
57
58
59
32
31
30
Vref
Audio I/F
Audio I/F
R
27
28
29
Vref
