Sharp HT-CN300H (serv.man4) Service Manual ▷ View online
– 41 –
HT-CN300H
IC710 RH-iX0489AWZZ: System Microcomputer (IX0489AW) (1/2)
1
P96/ANEX1/SOUT4
FLD_SDAT
Output
Display data output to M66005FP-FL driver.
2
P95/ANEX0/CLK4
FLD_SCK
Output
Serial clock output to M66005FP-FL driver.
3
P94/DA1/TB4IN
FLD_CS
Output
CS control output to M66005FP-FL driver.
4
P93/DA0/TB3IN
FLD_RESET
Output
Reset output to M66005FP-FL driver.
5*
P92/TB2IN/SOUT3
DVD_KDATA
Output
Control data output to the DVD unit.
6
P91/TB1IN/SIN3
DVD_DATA
Input
DVD/CD/VCD data input from the DVD unit.
7*
P90/TB0IN/CLK
DVD_CLK
Output
Serial clock output to the DVD unit.
8
BYTE
BYTE
Input
Connected to VSS due to unused external bus.
9
CNVSS
FLASH_VCC
Input
Used in the single chip mode. Connected to VSS via pull-down resistance.
10
P87/XCIN
DVD_STB
Input
Strobe input from the DVD unit.
11*
P86/XCOUT
DVD_ERITE
Output
“L” - DVD microcomputer ROM write mode.
12
RESET
RESET
Input
Microcomputer reset input. Active “L”.
13
XOUT
X_OUT
Output
Microcomputer reference oscillation output.
14
VSS
GND
—
Connected to GND (VSS).
15
XIN
X_IN
Input
Microcomputer reference oscillation input
16
VCC
VCC
Input
Microcomputer power supply (3.3 V)
17
P85/MNI
FLASH_"H"
Input
Connected to VCC via pull-up resistance.
18
P84/INT2
SYS_STOP
Input
Power failure detection input. Microcomputer enters the backup mode.
19
P83/INT1
GND
—
Port processing. “L” fixed.
20
P82/INT0
RX_IN
Input
Sharp method, remote control input..
21*
P81/TA4IN/U
TIMER_LED
Output
Timer stand-by LED control.
22
P80/TA40UT/U
DD_LED
Output
Dolby digital IND.
23
P77/AT3IN
STD_LED
Output
Surround mode stanrd IND.
24
P76/TA3OUT
DTS_LED
Output
DTS IND.
25
P75/TA2IN/W
VIR_LED
Output
Surround mode virtual IND.
26
P74/TA2OUT/W
AAC_LED
Output
AAC IND.
27
P73/CTS2/RT2S/TA1IN/V
DPL_LED
Output
Dolby pro logic IND.
28
P72/CLK2/TA1OUT/V
F-CONT2
Input
Switches power supply frequency and changes oscillation frequency.
29
P71/RXD2/SCL/TA0IN/TB5IN SCL
Output
AK4586/CXA2125Q. 12C BUS clock output.
30
P70/TXD2/SDA/TA0OUT SDA
Input/Output
AK4586/CXA2125Q. 12C BUS data input/output.
31
P67/TXD1
FLASH_TXD
Output
Functionally not used. Normally, output “L” fixed.
32
P66/RXD1
FLASH_RXD
Output
Functionally not used. Normally, output “L” fixed.
33
P65/CLK1
FLASH_SLOCK
Output
Functionally not used. Normally, output “L” fixed.
34
P64/CTS1/RTS1/CTS0/CLKS1
FLASH_BUSY
Output
Functionally not used. Normally, output “L” fixed.
35
P63/TXD0
DSP_SCDIN
Output
DSP IC serial data output.
36
P62/RXD0
DSP_SCDOUT
Input
DSP IC serial data output.
37
P61/CLK0
DSP_SCCLK
Output
Sends DSP IC serial send/receive sync clock.
38
P60/CTS0/RTS0
DSP_CS
Input
Sends DSP IC serial send/receive strobe.
39
P57/RDY/CLKOUT
DSP_RESET
Output
DSP IC RESET output.
40*
P56/ALE
L-MUTE
Output
VCR OUT audio mute output.
41
P55/HOLD
FLASH_EPM
Input
Connected to VSS via pull-down resistance.
42
P54/HLDA
AUDITION
Input
Audition model select input.
43*
P53/BCLK
F_CONT
Output
Switches power supply frequency and changes oscillation frequency.
44*
P52/RD
FM_STB
Output
When function is set to “FM Stereo” or “FM MONO”: “L”. Otherwise: “H”.
45
P51/WRH/BHE
DSP_UC15
Output
External ROM for DSP download program.
46
P50/WRL/WR
FLASH_CE
Input
Connected to VCC via pull-up resistance.
47
P47/CS3
DSP_UC16
Output
External ROM for DSP download program.
48
P46/CS2
DSP_UC17
Output
External ROM for DSP download program.
49
P45/CS1
ASPECT
Input
DVD unit aspect ratio data input.
50
P44/CS0
V-MODE
Input
Video mode select SW input terminal.
51*
P43/A19
V_SEL1
Output
Connected to video output selector, SW1.
Port Name
Terminal Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
HT-CN300H
– 42 –
52*
P42/A18
V_SEL2
Output
Connected to video output selector, SW2.
53*
P41/A17
V_SEL3
Output
Connected to video output selector, SW4.
54*
P40A16
V_SEL4
Output
Connected to video output selector, SW5.
55*
P37/A15
V_DATA
Output
Data output for electronic Vol IC control signal.
56*
P36/A14
VOL_STB
Output
Strobe output for electronic Vol IC control signal.
57*
P35/A13
VOL_CLK
Output
Clock output for electronic Vol IC control signal.
58*
P34/A12
DOOR_SPED
Output
DVD/CD door speed switch output
59*
P33/A11
DOOR_M+
Output
Control output of CD/DVD mechanism door OPEN/CLOSE control motor.
60*
P32/A10
DOOR_M-
Output
Control output of CD/DVD mechanism door OPEN/CLOSE control motor.
61
P31/A9
DOOR_OP
Input
CD/DVD mechanism door OPEN SW input.
62
VCC
VCC
Input
Microcomputer power supply (3.3 V).
63
PP30/A8(/-/D7)
DOOR_CL
Input
CD/DVD mechanism door CLOSE SW input.
64
VSS
GND
Output
Connected to GND (VSS).
65
P27/A7(/D7/D6)
ROM
Output
ROM/RAM enable control output on DSP PWB.
66
P26/A6(D6/D5)
DSP_AB00T
Output
DSP auto boot control terminal. Auto boot starts by “L” setting at DSP RESET.
67
P25/A5(/D5/D4)
OFFSET
Input
Detection input of 1-bit AMP
∆∑
IC’s output offset voltage error.
68*
P24/A4(/D4/D3)
A/D_RESET
Output
1-bit AMP’s
∆∑
IC reset control output.
69*
P23/A3(/D3/D2)
DVD_+B
Output
Output of power control and DIG signal switch to the DVD unit.
70*
P22/A2(/D2/D1)
DIG_FUNC+B
Output
Power control output for external DIG input.
71*
P21/A1(/D1/D0)
BASS-SW
Output
Output for subwoofer amp gain control.
72
P20/A0(/D0/-)
S_MUTE
Output
System mute control output.
73
P17/D15/INT5
A/D_REMONI
Input
1-bit AMP’s
∆∑
IC reset monitor output (Schmitt).
74
P16/D14/INT4
DSP_INTREQ
Input
DSP data reception request signal output.
75
P15/D13/INT3
H. P_SW
Input
Headphone SW detection input.
76*
P14/D12
-B_CONT
Output
1-bit AMP’s +B power control relay control output.
77*
P13/D11
FAN_MOTOR
Output
Output for cooling fan motor rotation control.
78
P12/D10
POWER
Output
Primary power relay control ouput.
79
P11/D9
W_SP_RLY
Output
Subwoofer speaker relay output.
80
P10/D8
S_SP_RLY
Output
Surround speaker relay output.
81
P07/D7
C_SP_RLY
Output
center speaker relay output.
82
P06/D6
F_SP_RLY
Output
Front speaker relay output
83
P05/D5
POWER_KEY
Input
Power operation key input.
84
P04/D4
TU_MUTE
Output
Tuner mute output.
85
P03/D3
CCB_DO
Input
Serial data input from Sanyo CCB device.
86*
P02/D2
CCB_CL
Output
Serial clock output from Sanyo CCB device
87*
P01/D1
CCB_DI
Output
Serial command data output from Sanyo CCB device
88*
P00/D0
CCB_CE
Output
CE control output from Sanyo CCB device.
89
P107/AN7/K13
TUNER_SM
Input
A/D downloading, field strength comparison detect input.
90
P106/AN6/K12
SD_ST_IN
Input
A/D downloading. Tuner tuning, stereo signal detect..
91
P105/AN5/K1
PROTECT
Input
A/D downloading. System error detection input.
92
P104/AN4/KI0
AREA
Input
A/D downloading. Destination setup for tuner band.
93
P103/AN3
TV_TYPA
Input
Sets the TV type by A/D downloading.
94
P102/AN2
DOOR_PROT
Input
Finger pinching detection input by CD/DVD mechanism door.
95
P101/KEY2
AVSS
Input
A/D downloading, main unit key input 2.
96
AVSS
GND
Input
VSS terminal of A/D converter.
97
P100/ANP/
KEY1
Input
A/D downloading, main unit key input 1.
98
PVREF
VREF
Input
Reference voltage input terminal of A/D converter.
99
AVCC
AVCC
Input
Power supply input terminal of A/D converter.
100
P97/ADTRG/SIN 4
GND
Input
Port processing. “L” fixed. (Not used.).
IC710 RH-iX0489AWZZ: System Microcomputer (IX0489AW) (2/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Port Name
Terminal Name
Pin No.
Input/Output
Function
– 43 –
HT-CN300H
IC708 VHIAK4586VQ-1: ADC/DAC/DIR Converter (AK4586VQ)
1*
XTO
OUtput
Crystal vibrator output.
2
XTI
Input
Crystal vibrator input.
EXTCLE
Input
Master clock input.
3
TVDD
Input
Power supply for output buffer, 2.7-5.5 V.
4
DVSS
—
Digital GND pin, 0 V.
5
DVDD
Input
Digital power supply, 4.5-5.5 V.
6*
TX
Output
Transmit channel (through data) output.
7
MCKO
Output
Master clock output.
8
LRCK
Input/Output
Input/output channel clock.
9
BICK
Input/Output
Audio serial data clock.
10
SDTO
Output
Audio serial data output.
11
SDTI 1
Input
DAC 1 audio serial data input.
12
SDTI 2
Input
DAC 2 audio serial data input.
13
SDTI 3
Input
DAC 3 audio serial data input.
14*
INT 0
Output
Interrupt 0.
15*
INT 1
Output
Interrupt 1.
16
CDTO
Output
Control data output.
CAD 1
Input
Chip address 1.
17
CDTI
Input
Control data input.
SDA
Input/Output
Control data input/output.
18
CCLK
Input
Control data clock.
SCL
Input
Control data clock.
19
CNS
Input
Chip select.
CAD 0
Input
Chip address 0
20*
DZF 2
Output
Zero input detect 2. (Note 1)
When input data in the group 2 is “0” continuously over 8192 times or RSTN bit is “0”: “H”.
When input data in the group 2 is “0” continuously over 8192 times or RSTN bit is “0”: “H”.
OVF
Output
Analog input overflow detect. (Note 1)
When analog input of Lch or Rch overflows: “H”
When analog input of Lch or Rch overflows: “H”
21
AVSS
—
Analog GND pin, 0 V.
22
AVDD
Input
Analog power supply, 4.5-5.5 V.
23
VREFH
Input
Reference voltage input, AVDD.
24
VCOM
Output
Common voltage output, AVDD/2.
25*
DZF1
Output
Zero input detect.
26
LOUT 3
Output
DAC 3 L channel analog output.
27
ROUT 3
Output
DAC 3 R channel analog output.
28
LOUT 2
Output
DAC 2 L channel analog output.
29
ROUT 2
Output
DAC 2 R channel analog output.
30
LOUT 1
Output
DAC 1 L channel analog output.
31
ROUT 1
Output
DAC 1 L channel analog output.
32
LIN
Input
L channel analog input.
33
RIN
Input
R channel analog input.
34
PVDD
Input
PLL power supply, 4.5-5.5 V.
35
R
—
External resistance.
36
PVSS
—
PLL GND pin, 0 V.
37
RX4
Input
Receiver channel input 4 (internal bias pin).
38
SLAVE
Input
Slave mode.
39*
RX2
Input
Receiver channel input 3 (internal bias pin).
40
TST
Input
Test pin.
41
RX2
Input
Receiver channel input 2 (internal bias pin).
42
I2C
Input
Serial control mode select.
43*
RX1
Input
Receiver channel input 1 (internal bias pin).
44
PDN
Input
Power down & reset.
Port Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
HT-CN300H
– 44 –
FL690 VVKHNA9SS32-1
FL DISPLAY
1G
2G
4G
5G
6G
7G
8G
9G
3G
BYPASS
NORMAL
PHANTOM MEMORY
SLEEP
X-BASS
ST
dts
kHz
MHz
MHz
ms
dB RDS TP TA
DIGITAL
VIRTUAL
PRO LOGIC
PRO LOGIC
PTYI RT
c o l
S1
S2
S3
S4
a
h
f
j
k
b
m
g
e
r
p
d
( 1G - 8G )
Dp
n
c
P1
P2
P3
P4
P5
P5
P6
P7
P8
P9
P7
P8
P9
P10
P11
P12
P12
P13
P14
P15
P16
P17
P14
P15
P16
P17
P18
P19
P20
P19
P20
1G
S2
BYPASS
S1
S3
S4
S4
a
b
k
b
k
j
h
f
m
d
g
p
g
p
e
n
n
r
c
Dp
2G
NORMAL
S2
S1
S3
S4
S4
a
b
k
b
k
j
h
f
m
d
g
p
g
p
e
n
n
r
c
Dp
3G
S2
S1
S3
S4
S4
a
b
k
b
k
j
h
f
m
d
g
p
g
p
e
n
n
r
c
Dp
4G
PHANTOM
S2
S1
S3
S4
S4
a
b
k
b
k
j
h
f
m
d
g
p
g
p
e
n
n
r
c
Dp
5G
MEMORY
S2
S1
S3
S4
S4
a
b
k
b
k
j
h
f
m
d
g
p
g
p
e
n
n
r
c
Dp
6G
S2
S1
S3
S4
S4
a
b
k
b
k
j
h
f
m
d
g
p
g
p
e
n
n
r
c
Dp
7G
S2
col
S1
S3
S4
S4
a
b
k
b
k
j
h
f
m
d
g
p
g
p
e
n
n
r
c
Dp
8G
9G
SLEEP
PTYI
TA
TP
RDS
RT
ST
X-BASS
dts
kHz
MHz
ms
dB
PRO LOGIC
S2
S1
S3
S4
S4
a
b
k
b
k
j
h
f
m
d
g
p
g
p
e
n
n
r
c
Dp
PRO LOGIC
VIRTUAL
DIGITAL
ANODE CONNECTION
GRID ASSIGNMENT
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