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FV-DB1E
7 – 1
Audio
FV-DB1E
Service Manual
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CHAPTER 7.
OTHER
[1] Function table of IC
TUN1 RTUNSA001SJZZ: DAB Unit
1. FS2020 (VENICE) MODULE OVERVIEW
1.1. Introduction
The FS2020 (Venice) module has been developed as an OEM module,
which will enable low cost Band only DAB receivers. All that is
required to produce a low cost Digital Radio is a power source,
antenna, LCD and Keypad. Alternatively the module can be pro-
grammed to operate in ‘slave’ mode under the control of an existing
microcontroller. The module has been designed for use in static, porta-
ble and car audio products.
which will enable low cost Band only DAB receivers. All that is
required to produce a low cost Digital Radio is a power source,
antenna, LCD and Keypad. Alternatively the module can be pro-
grammed to operate in ‘slave’ mode under the control of an existing
microcontroller. The module has been designed for use in static, porta-
ble and car audio products.
Reference software can be provided for both master (Reference MMI),
or slave (Serial Interface) applications.
or slave (Serial Interface) applications.
1.2. Features
A block diagram of the Module is shown in Figure 7-1. The main com-
ponents are Band RF frontend, FS1010 (Chorus) DAB baseband
processor, a serial boot FLASH and audio DAC. As an option SDRAM
can be fitted to support advanced applications. External components
that may be connected to the module are shown as grey blocks in Fig-
ure 7-1.
ponents are Band RF frontend, FS1010 (Chorus) DAB baseband
processor, a serial boot FLASH and audio DAC. As an option SDRAM
can be fitted to support advanced applications. External components
that may be connected to the module are shown as grey blocks in Fig-
ure 7-1.
NOTE: 5 V rail is connected to RF section only and care should be
taken to provide a clean, decoupled supply to ensure that the
RF sensitivity is not degraded.
RF sensitivity is not degraded.
An on-board SPI port supports a serial boot FLASH device. A dedi-
cated port is provided for direct connection to an LCD, general-purpose
I/O lines are provided for keypad scanning, shaft encoder input and
control of simple circuits.
cated port is provided for direct connection to an LCD, general-purpose
I/O lines are provided for keypad scanning, shaft encoder input and
control of simple circuits.
Hardware interfaces include USB ports, and a serial host port for con-
nection to a controlling CPU.
nection to a controlling CPU.
Stereo audio output is available in S/PDIF digital formats, as well as
line level. Multi-channel audio output is available via the I
line level. Multi-channel audio output is available via the I
2
S port, while
PCM or compressed audio can be input to CHORUS via the S/PDIF
input.
input.
The FS1010 (Chorus) processor is based around Imagination Technol-
ogies' META advanced RISC/DSP. In addition to running the core DAB
demodulation functions, this processor is well suited to running the
application code, which receiver manufacturers will add on top of the
core DAB processing to produce complete products. The core DAB
functions require less than one third of the processing capacity of
META, leaving considerable scope for application processing.
ogies' META advanced RISC/DSP. In addition to running the core DAB
demodulation functions, this processor is well suited to running the
application code, which receiver manufacturers will add on top of the
core DAB processing to produce complete products. The core DAB
functions require less than one third of the processing capacity of
META, leaving considerable scope for application processing.
2. HARDWARE INTERFACES
The FS2020 (Venice) module has a number of hardware interfaces,
designed to support a range of DAB applications. The characteristics
of these interfaces are detailed below.
designed to support a range of DAB applications. The characteristics
of these interfaces are detailed below.
2.1. RF Input
There are two connectors available that can be used to carry VHF (174
MHz to 240 MHz) for Band Only. These are a 2.6 mm UMP type and
2.54 mm pitch holes to be used with a header or for direct soldering of
an RF cable.
MHz to 240 MHz) for Band Only. These are a 2.6 mm UMP type and
2.54 mm pitch holes to be used with a header or for direct soldering of
an RF cable.
2.2. Analogue Audio output
Stereo line level outputs are provided using the on-board stereo audio
DAC.
DAC.
2.3. Digital Audio Input/Output (I
2
S)
Seven signal wires (master clock, bit clock, sample frame, stereo in, 6
channel out) carry digital audio input and multi-channel output to an
external DAC or CODEC. The multi-channel output may be used for
home cinema applications including Dolby Digital and DTS.
channel out) carry digital audio input and multi-channel output to an
external DAC or CODEC. The multi-channel output may be used for
home cinema applications including Dolby Digital and DTS.
2.4. S/PDIF Audio Output
The S/PDIF audio output carries a stereo digital audio output on a sin-
gle wire using the signal format defined in IEC60958.
gle wire using the signal format defined in IEC60958.
2.5. S/PDIF Input
The S/PDIF input accepts digital audio data on a single wire using the
signal format defined in IEC60958. This input may also be used as an
input for CD-ROM data including MP3 encoded date.
signal format defined in IEC60958. This input may also be used as an
input for CD-ROM data including MP3 encoded date.
2.6. RDI Output
The RDI output carries a an RDI signal conforming to Specification of
the Receiver Data Interface (RDI) - Eureka 147 Project - Issue 1. 4
November 1996 on a single wire using the signal format defined in
IEC60958. If an output is not required, then this line may be used as
GPIO.
the Receiver Data Interface (RDI) - Eureka 147 Project - Issue 1. 4
November 1996 on a single wire using the signal format defined in
IEC60958. If an output is not required, then this line may be used as
GPIO.
Figure 7-1 VENICE MODULE BLOCK DIAGRAM
(Functions in white are on board, in grey are external)
FS1010
(Chorus)
384KB
RAM
LCD
External
DAC or
CODEC
SDRAM
(optional)
Audio
DAC
Band III
RF
5V
Serial
Flash
Keypad/
Rotary
encoder
USB
I/face
Serial
I/Faces
S/PDIF
& RDI
I/faces
Input impedance:
50 R, nominal
VSWR
2.0, maximum
Max power:
0 dBm
Sensitivity:
(signal level required for 10
(signal level required for 10
-4
BER with 1/2 rate coding) -96 dBm
Adjacent Channel Rejection
(for 10
(for 10
-4
BER with 1/2 rate coding)
35 dB minimum
Sample rate:
48 kHz
Master clock rate:
512 x sample rate (24.576 MHz)
Sample resolution:
16, 18, 20 or 24 bits (controlled by software).
Sample rate:
48 kHz
Sample resolution:
24 bits
Sample rate:
48 kHz
RDI format:
high capacity
FV-DB1E
7 – 2
2.7. Asynchronous Serial Port
The asynchronous serial port carries asynchronous serial characters
over two wires (TxD, RxD) at data rates up to 115 kbit/s. In this particu-
lar application it can be used to control the module in ‘slave’ mode.
The default baud rate is 115 kbit/s.
over two wires (TxD, RxD) at data rates up to 115 kbit/s. In this particu-
lar application it can be used to control the module in ‘slave’ mode.
The default baud rate is 115 kbit/s.
2.8. Universal Serial Bus
A USB 1.1 interface (slave) is carried over two wires. The USB inter-
face will support data transfers at up to 12 Mbits/s.
face will support data transfers at up to 12 Mbits/s.
2.9. Serial Control Bus (I
2
C)
The Serial Control Bus consists of a two wire, open collector bus. This
bus is a master only, and may be used for controlling other devices in
the system.
bus is a master only, and may be used for controlling other devices in
the system.
2.10. PDM output
A single PDM (Pulse Density Modulated) output can be provided for
generation of a low resolution analogue output. This may be used for
control of display brightness for example.
generation of a low resolution analogue output. This may be used for
control of display brightness for example.
2.11. LCD Port
LCD display data is presented on 8 data lines, with 4 timing control
lines to synchronize transfers. The LCD port will support both alphanu-
meric and graphic LCDs. If a LCD connection is not required, then
these lines may be used as GPIO.
lines to synchronize transfers. The LCD port will support both alphanu-
meric and graphic LCDs. If a LCD connection is not required, then
these lines may be used as GPIO.
NOTE: Ideally, the LCD controller should be powered from the 3V3
supply. If a 5 V LCD module is used it should have its own
supply rail and should not be connected to the 5 V RF supply
as any conducted noise will degrade RF sensitivity.
supply rail and should not be connected to the 5 V RF supply
as any conducted noise will degrade RF sensitivity.
2.12. General Purpose I/O
All the above signals (excluding USB, I
2
S control and stereo out) may
be used as GPIO signals. The state of each GPIO signal can be read
by software. The logic level and tri-state drive of each GPIO signal can
also be controlled by software.
by software. The logic level and tri-state drive of each GPIO signal can
also be controlled by software.
The following table specifies the main pin functions, identifies which of
these can be used as GPIO lines, and also defines an example DAB
product function based on the reference MMI software.
these can be used as GPIO lines, and also defines an example DAB
product function based on the reference MMI software.
The Reference MMI software assigns the following button mapping for
the keypad matrix:
the keypad matrix:
Alphanumeric mode: 4-bit or 8-bit data transfers.
Compatible with displays using Hitachi
HD44780, Samsung S6A0069X (KS0066) or
similar controllers.
HD44780, Samsung S6A0069X (KS0066) or
similar controllers.
Graphic mode:
4-bit or 8-bit data transfers.
4 control signals (date clock, line clock, frame
clock, polarity reversal) compatible with wide
range of graphic display controllers.
4 control signals (date clock, line clock, frame
clock, polarity reversal) compatible with wide
range of graphic display controllers.
Main Function
GPIO
CN1 pin
number
Reference MMI
Implementation
S/PDIF Output
A11
12
S/PDIF Output
S/PDIF Input
A0
37
Keypad row 3
RDI Output
A10
38
Keypad row 4
S1_DIN
D3
15
S1_DOUT
D2
16
USB_DP
No
9
USB_DP
USB_DM
No
8
USB_DM
SCP_CLK
A9
39
IR remote activity LED
SCP_DAT
A8
40
IR receiver input
PDM Output
A7
41
Keypad column 3
LCD_DATA<7..0>
B<15..8>
25-32
LCD_DATA<7..0>
LCD_F
C1
33
Keypad row 2
LCD_LRS
C2
34
LCD_RS
LCD_M
C0
35
Keypad row 1
LCD_PE
C3
36
LCD_E
AUD_SFR
No
21
AUD_SFR
AUD_SCLK
No
23
AUD_SCLK
AUD_MCLK
No
24
AUD_MCLK
AUD_SDOUT0
No
22
AUD_SDOUT0
AUD_SDOUT1
A1
42
Keypad column 1
AUD_SDOUT2
A2
43
Keypad column 2
AUD_SDIN
A12
44
Keypad column 4
Column 1
Column 2
Column 3
Column 4
Row 1
scroll_up
scroll_down
Select
preset 1
Row 2
display
info
Scan
preset 2
Row 3
volume_up
volume_down Mute
preset 3
Row 4
power
factory_rst
preset 4
preset 5
FV-DB1E
7 – 3
IC401 RH-iXA021SJZZ: System Microcomputer (IXA021SJ) (1/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Port Name
Terminal Name
Input/Output
Function
1
P50/A8
A_MUTE
Output
AUDIO MUTE control output. “L”: MUTE OFF “H”: MUTE ON
2*
P51/A9
NO USE
—
Not used. (fixed to Low as output pin)
3
P52/A10
PLL_CE
Output
Output pin for enabling TUNER IC LV23002 chip.
4
P53/A11
VOL_CE
Output
Output pin for enabling Volume IC LC75341 chip.
5
P54/A12
LINE_MUTE
Output
LINE MUTE control output. “L”: MUTE OFF “H”: MUTE ON
6*
P55/A13
DAB
Output
DAB RF IN control output. “H”: No RF IN “L”: RF IN
7
P56/A14
DAB POWER
Output
DAB power supply control output. “H”: OFF “L”: ON
8*
P57/A15
NO USE
—
Not used. (fixed to Low as output pin)
9
VSS0
VSS0
—
PORT GND.
10
VDD0
VDD0
Input
PORT power supply. (3.3 V)
11*
P30
NO USE
—
Not used. (fixed to Low as output pin.)
12*
P31
NO USE
—
Not used. (fixed to Low as output pin.)
13*
P32/SDA0
NO USE
—
Not used. (fixed to Low as output pin.)
14*
P33/SCL0
NO USE
—
Not used. (fixed to Low as output pin.)
15
P34/SI3/TxD2
TX
Output
Not used functionally. Normally fixed to output “L”.
(Output for received data from FLASH writer.)
(Output for received data from FLASH writer.)
16
P35/SO3/RxD2
RX
Input
Not used functionally. Normally fixed to output “L”.
(Input for received data from FLASH writer.)
(Input for received data from FLASH writer.)
17
P36/SCK3/ASCK2
SCK
Input
Not used functionally. Normally fixed to output “L”.
(Input for transfer clock from FLASH writer.)
(Input for transfer clock from FLASH writer.)
18
P20/SI1
DO
Input
Input pin for receiving tuner communication data. TUNER
→System
19
P21/SO1
DI
Output
Output for sending TUNER/Volume/LCD communication command data.
System
System
→TUNER/Volume/LCD
20
P22/SCK1
CLK
Output
Output pin for TUNER/Volume/LCD communication synchronous clock.
Synchronous fall
Synchronous fall
21
P23/RxD0
S1_DIN
Input
Input pin for receiving DAB UNIT communication data.
DAB UNIT
DAB UNIT
→System
22
P24/TxD0
S1_DOUT
Output
Output for sending DAB UNIT communication command data.
System
System
→DAB UNIT
23
P25/ASCK0
SCP_CLK
Input
Input pin for DAB UNIT communication synchronous clock.
Synchronous rise
Synchronous rise
24
VDD1
VDD1
Input
Power supply. (3.3 V) (except for PORT.)
25
AVSS
AVSS
—
A/D converter GND. (connected to VSS. A/D converter not used.)
26*
P17/ANI7
NO USE
—
Not used. (fixed to Low as output pin.)
27*
P16/ANI6
NO USE
—
Not used. (fixed to Low as output pin.)
28*
P15/ANI5
NO USE
—
Not used. (fixed to Low as output pin.)
29*
P14/ANI4
NO USE
—
Not used. (fixed to Low as output pin.)
30*
P13/ANI3
NO USE
—
Not used. (fixed to Low as output pin.)
31
P12/AN12
AD2
Input
A/D capture, main unit key input 2.
32
P11/AN11
AD1
Input
A/D capture, main unit key input 1.
33
P10/AN10
AD0
Input
A/D capture, main unit key input 0.
34
AVREF
AV_REF
Input
A/D converter power supply. (connected to VSS. A/D converter not used.)
35*
P80/SS1
NO USE
—
Not used. (fixed to Low as output pin.)
36
RESET
RESET
Input
Microcomputer reset input. Active “H”.
Connected to FLASH writer’s RESET line when writing.
Connected to FLASH writer’s RESET line when writing.
37
XT2
XT2
Output
Sub clock output. 32.768 kHz crystal oscillator connection.
38
XT1
XT1
Input
Sub clock input. 32.768 kHz crystal oscillator connection.
39
IC (VPP)
IC (VPP)
—
Flash memory pin. External PULL DOWN at 10 kohm.
40
X2
X2
Output
Main clock output. 8.38 MHz crystal oscillator connection.
41
X1
X1
Input
Main clock input. 8.38 MHz crystal oscillator connection.
42
VSS1
VSS1
—
GND (except for PORT.)
43
P00/INTP0
PWR_DET
Input
AC adaptor detection. “H”: AC adapter
44
P01/INTP1
PON_DET
Input
POWER key input. “L”: POWER OFF “H”: POWER ON
45
P02/INTP2
P_SUPPLY
Input
Input pin for detecting battery connection.
“L”: Battery connected. “H”: Not connected.
“L”: Battery connected. “H”: Not connected.
46*
P03/INTP3/ADTRG
NO USE
—
Not used. (fixed to Low as output pin.)
47*
P70/TI000/TO00
STB
Output
Chip select control output to LCD driver.
48*
P71/TI010
NO USE
Output
Not used. (fixed to Low as output pin.)
49
P72/TI50/TO50
NO USE
Output
Not used. (fixed to Low as output pin.)
50
P73/TI51/TO51
NO USE
—
Not used. (fixed to Low as output pin.)
51*
P74/PCL/TI011
NO USE
—
Not used. (fixed to Low as output pin.)
52
P75/BUZ/TI001/TO01
BUZ
Output
Buzzer output pin.
FV-DB1E
7 – 4
IC401 RH-iXA021SJZZ: System Microcomputer (IXA021SJ) (2/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Port Name
Terminal Name
Input/Output
Function
53
P64/RD
DIMMER_1
Output
DIMMER_1 control output.
54
P65/WR
DIMMER_2
Output
DIMMER_2 control output.
55*
P66/WAIT
NO USE
—
Not used. (fixed to Low as output pin.)
56
P67/ASTB
TIMER_LED
Output
TIMER LED control output. “H”: TIMER ON “L”: TIMER OFF
57*
P40/AD0
NO USE
—
Not used. (fixed to Low as output pin.)
58*
P41/AD1
NO USE
—
Not used. (fixed to Low as output pin.)
59*
P42/AD2
NO USE
—
Not used. (fixed to Low as output pin.)
60*
P43/AD3
NO USE
—
Not used. (fixed to Low as output pin.)
61*
P44/AD4
NO USE
—
Not used. (fixed to Low as output pin.)
62*
P45/AD5
NO USE
—
Not used. (fixed to Low as output pin.)
63*
P46/AD6
NO USE
—
Not used. (fixed to Low as output pin.)
64*
P47/AD7
NO USE
—
Not used. (fixed to Low as output pin.)
A_MUTE
1
2 P51/A9
2 P51/A9
P50/A8
PLL_CE
3 P52/A10
VOL_CE
4 P53/A11
LINE_MUTE
5 P54/A12
DAB
6 P55/A13
DAB POWER
7 P56/A14
8 P57/A15
8 P57/A15
VSS0
9 VSS0
VDD0
10 VDD0
11 P30
12 P31
13 P32/SDA0
14 P33/SCL0
11 P30
12 P31
13 P32/SDA0
14 P33/SCL0
TX
15 P34/SI3/TxD2
RX
16 P35/S03/RxD2
SCK
17
P36/SCK3/ ASCK2
DO
18
P20/SI1
DI
19
P21/S01
CLK
20
P22/SCK1
S1_DIN
21
P23/RxD0
S1_DOUT
22
P24/TxD0
SCP_CLK
23
P25/ASCK0
VDDI
24
VDD1
AVSS
25
AVSS
26
P17/ANI7
27
P16/ANI6
28
P15/ANI5
29
P14/ANI4
30
P13/ANI3
AD2
31
P12/ANI2
AD1
32
P11/ANI1
48
STB
47
P70/TI000/
T000
46
P03/INTP3/
ADTRG
P_SUPPLY
45
P02/INTP2
PON_DET
44
P01/INTP1
PWR_DET
43
P00/INTP0
VSS1
42
VSS1
X1
41
X1
X2
40
X2
IC(VPP)
39
IC(VPP)
XT1
38
XT1
XT2
37
XT2
RESET
36
RESET
35
P80/SS1
AV_REF
34
AVREF
ADO
33
P10/ANI0
64
P47/AD7
63
P46/AD6
62
P45/AD5
61
P44/AD4
60
P43/AD3
59
P42/AD2
58
P41/AD1
57
P40/AD0
TIMER_LED
56
P67/ASTB
55
P66/WAIT
DIMMER_2
54
P65/WR
DIMMER_1
53
P64/RD
BUZ
52
P75/BUZ/TI001/T001
51
P74/PCL/TI011
50
P73/TI51/T051
49
P72/TI50/
T050
P71/TI010
IXA021SJ
Figure 7-4 BLOCK DIAGRAM OF IC
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