Sharp CD-XP700H (serv.man18) Service Manual ▷ View online
– 45 –
CD-XP700H
IC3 VHiLC78683E-1: MP3 Decoder (LC78683E) (1/2)
1
LRSK
Input
CD L/R clock input.
2
ADDATA
Output
Audio data output.
3
ADBCK
Output
Audio bit clock output.
4
ADLRCK
Output
Audio L/R clock output.
5
C2FIN
Input
CD C2 error flag input.
6
TEST1
Input
Test input 1. (Must be connected to GND.)
7
CKIN
Input
System clock (16.9344 MHz) input.
8
VSS
—
GND ground pin.
9
CKOUT
Output
External DF/DAC clock (384Fs) output.
10
TEST2
Input
Test input 2. (Must be connected to GND.)
11
DVDD1
Input
I/O digital supply pin.
12
PW
Input
CD subcode data serial input.
13
SBSY
Input
CD subcode block synchronization signal input.
14
SFSY
Input
CD subcode frame synchronization signal input.
15*
SBCK
Output
CD subcode transfer serial clock output.
16
AVDD
Input
Analog (PLL) supply.
17
VPRER
—
VCO oscillator range set pin.
18
VCOC
Input
VCO control voltage input.
19
VPDO
Output
VCO charge pump output.
20
AVSS
—
Analog GND ground pin.
21
DVDD2
Input
Internal logic supply pin.
22
VSS
—
GND ground pin.
23
MDATA0
Input/Output
DRAM data bus 0.
24
MDATA1
Input/Output
DRAM data bus 1.
25
MDATA2
Input/Output
DRAM data bus 2.
26
MDATA3
Input/Output
DRAM data bus 3.
27
MDATA4
Input/Output
DRAM data bus 4.
28
MDATA5
Input/Output
DRAM data bus 5.
29
MDATA6
Input/Output
DRAM data bus 6.
30
MDATA7
Input/Output
DRAM data bus 7.
31
DVDD3
Input
I/O digital supply pin.
32
VSS
—
GND ground pin.
33
MDATA8
Input/Output
DRAM data bus 8.
34
MDATA9
Input/Output
DRAM data bus 9.
35
MDATA10
Input/Output
DRAM data bus 10.
36
MDATA11
Input/Output
DRAM data bus 11.
37
MDATA12
Input/Output
DRAM data bus 12.
38
MDATA13
Input/Output
DRAM data bus 13.
39
MDATA14
Input/Output
DRAM data bus 14.
40
MDATA15
Input/Output
DRAM data bus 15.
41
RASB
Output
RAS output. (L-active)
42
WEB
Output
WE output. (L-active)
43
CASLB
Output
CAS output. (Lower Byte, L-active)
44
CASUB
Output
CAS output. (Upper Byte, L-active)
45
OEB
Output
OE output (L-active)
46*
MADRS12
Output
DRAM address output 12.
47*
MADRS11
Output
DRAM address output 11.
48*
MADRS10
Output
DRAM address output 10.
49*
MADRS9
Output
DRAM address output 9.
50
MADRS8
Output
DRAM address output 8.
Terminal Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
CD-XP700H
– 46 –
IC3 VHiLC78683E-1: MP3 Decoder (LC78683E) (2/2)
51
DVDD4
Input
I/O digital supply pin.
52
VSS
—
GND ground pin.
53
MADRS7
Output
DRAM address output 7.
54
MADRS6
Output
DRAM address output 6.
55
MADRS5
Output
DRAM address output 5.
56
MADRS4
Output
DRAM address output 4.
57
MADRS3
Output
DRAM address output 3.
58
MADRS2
Output
DRAM address output 2.
59
MADRS1
Output
DRAM address output 1.
60
MADRS0
Output
DRAM address output 0.
61
DVDD5
Input
Internal logic supply pin.
62
VSS
—
GND ground pin.
63*
STREQ
Input/Output
MP3 data demand flag output. (H-active)/DRAM data demand flag input. (H-active)
64*
STCK
Input/Output
MP3 data transfer clock input./DRAM data transfer clock output.
65*
STDAT
Input/Output
MP3 data serial input./DRAM data serial output.
66
FSYNC
Output
MP3 frame synchronization signal. (H-active)
67*
CRCF
Output
CDROM-CRC flag output. (H-active)/DRAM data output enable signal output. (H-active)
68
DVDD6
Input
I/O digital supply pin.
69
VSS
—
GND ground pin.
70*
WOK
Input
DRAM write permit input. (CD-DA, H-active)/DRAM data demand flag input.
(CDROM, H-active)
(CDROM, H-active)
71*
CNTOK
Output
Data connection point detection completion flag. (CD-DA, H-active)/DRAM data serial
output. (CDROM, H-active)
output. (CDROM, H-active)
72*
OVF
Output
DRAM write interrupt flag. (CD-DA, H-active)/DRAM data transfer clock output.
(CDROM, H-active)
(CDROM, H-active)
73
CMDOUT
Output
Command serial data output. (Nch open drain output pin)
74
CMDIN
Input
Command serial data input.
75
CL
Input
Command serial clock input.
76
CE
Input
Command enable input. (H-active)
77
INTB
Output
Interrupt signal output. (L-active)
78
RESB
Input
System reset. (L-active)
79
DATAIN
Input
CD serial data input.
80
DATACK
Input
CD bit clock input.
Terminal Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
*1: Unused port
Unused input pin must always be connected to GND (0 V).
Unused output pin must be left open.
Unused I/O pin must either be connected to GND (0 V) or set to the output and left open.
Unused output pin must be left open.
Unused I/O pin must either be connected to GND (0 V) or set to the output and left open.
*2: Be sure to supply the same potential to DVDD1, DVDD3, DVDD4, DVDD6 and AVDD.
Power supply to DVDD2 and DVDD5 must always be lower than that for DVDD1.
*3: Be sure to connect input pins TEST1 and TEST2 to GND (0 V).
*4: I/O pins (MDATA0 to 15, STREQ, STCK, STDAT) are in the input mode during initialization.
*5: At power ON, be sure to set the RESB pin to "L" (1
*4: I/O pins (MDATA0 to 15, STREQ, STCK, STDAT) are in the input mode during initialization.
*5: At power ON, be sure to set the RESB pin to "L" (1
µ
s or more).
*6: It is necessary to supply to the CKIN pin the 16.9344 MHz clock from LSI for CD-DSP.
The oscillator circuit cannot be made up from this LSI and oscillator only.
– 47 –
CD-XP700H
IC3 VHiLC78683E-1: MP3 Decoder (LC78683E)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 26
27
28 29 30
31 32
33 34 35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
LRSY
ADDATA
ADBCK
ADLRCK
C2FIN
TEST1
CKIN
VSS
CKOUT
TEST2
DVDD1
PW
SBSY
SFSY
SBCK
AVDD
VPRFR
VCOC
VPDO
ACSS
DVDD2
VSS
MDATA0
MDATA1
MDATA2
MDATA3
MDATA4
MDATA5
MDATA6
MDATA7
DVDD3
VSS
MDATA8
MDATA9
MDATA10
MDATA11
MDATA12
MDATA13
MDATA14
MDATA15
DATACK
DATAIN
RESB
INTB
CE
CL
CMDIN
CMDOU
OVF
CNTOK
WOK
VSS
DVDD6
CRCF
FSYNC
STDAT
STCK
STREQ
VSS
DVDD5
MADRS0
MADRS1
MADRS2
MADRS3
MADRS4
MADRS5
MADRS6
MADRS7
VSS
DVDD4
MADRS8
MADRS9
MADRS10
MADRS11
MADRS12
OEB
CASUB
CASLB
WEB
RASB
LC78683E
Figure 47 BLOCK DIAGRAM OF IC
CD-XP700H
– 48 –
IC4 VHiLC32V4265B1: 4M (262144 words x 16 bits) DRAM (LC32V4265B)
1
VCC
Power supply.
2-5
I/O1-I/O4
Data I/O.
6
VCC
Power supply.
7-10
I/O5-I/O10
Data I/O.
11*-14*
N.C.
Not used.
15
WE
Write enable.
16
RAS
Low address strobe.
17*
N.C.
Not used.
18-21
A1-A3
Address input.
22
VCC
Power supply.
23
VSS
Ground
24-28
A4-A8
Address input.
29
OE
Output enable.
30
UCAS
Column address strobe. (Lower byte control)
31
LCAS
Column address strobe. (Upper byte control)
32*-34*
N.C.
Not used.
35-38
I/O9-I/O12
Data I/O.
39
VSS
Ground
40-43
I/O13-I/O16
Data I/O.
44
VSS
Ground
Terminal Name
Pin No.
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
RAS
UCAS
Clock generator No. 1
Clock generator No. 2
LCAS
A0
A8
Mode control
Refresh counter
Low address
buffer
Column
address buffer
Row decoder
262144 memory cells
x 16 bits
512
512x16
512
Sense ampllfler I/O gate
Column decoder
Pre-decoder
Substrate bias generator
Clock generator No. 3
Lower byte
Upper byte
Data input buffer
I/O1 to I/O8
I/O9 to I/O16
Data output buffer
I/O1 to I/O8
I/O9 to I/O16
OE
I/O16
I/O1
WE
VSS
VCC
1
2
3
4
5 6 7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VCC
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
N.C.
N.C.
N.C.
N.C.
WE
RAS
N.C.
A0
A1
A2
A3
VCC
VSS
I/O16
I/O15
I/O14
I/O13
VSS
I/O12
I/O11
I/O10
I/O9
N.C.
N.C.
N.C.
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS
Figure 48 BLOCK DIAGRAM OF IC
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