Sharp CD-MPX880H Service Manual ▷ View online
CD-MPX880H
8 – 1
CHAPTER 8. OTHERS
[1] Function Table Of IC
IC1 VHiLC78690E-1: CD Servo (LC78690E) (1/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal Name
Input/Output
Setting in Reset
Function
1
EFMIN
Input
INPUT
RF signal input pin.
2
RFOUT
Output
UNSTABLE
RF signal output pin.
3
LPF
Output
UNSTABLE
RF signal DC level detection. LPF capacitor connection pin.
4
PHLPF
Output
UNSTABLE
LPF capacitor pin for detection problem.
5
AIN
Input
INPUT
A signal input pin.
6
CIN
Input
INPUT
C signal input pin.
7
BIN
Input
INPUT
B signal input pin.
8
DIN
Input
INPUT
D signal input pin.
9
FEC
Output
UNSTABLE
FE signal LPF capacitor connection pin.
10*
RFMON
Output
UNSTABLE
Built in analog signal for monitoring LSI pin.
11
VREF
Output
AVDD/2
VREF voltage output pin.
12
JITTC
Output
UNSTABLE
Jitter detection capacitor connection pin.
13
EIN
Input
INPUT
E signal input pin.
14
FIN
Input
INPUT
F signal input pin.
15
TEC
Output
UNSTABLE
TE signal LPF capacitor connection pin.
16
TE
Output
UNSTABLE
TE signal output pin.
17
TEIN
Input
INPUT
TES signal generation TE signal input pin.
18
LDD
Output
UNSTABLE
Laser power control signal output pin.
19
LDS
Input
INPUT
Laser power control signal input pin.
20
AVSS
—
—
Analog GND pin. This pin must always be connected to 0V.
21
AVDD
—
—
Analog power supply pin.
22
FDO
Output
AVDD/2
Focus control output pin. D/A converter output.
23
TDO
Output
AVDD/2
Tracking control output pin. D/A converter output.
24
SLDO
Output
AVDD/2
SLED control output pin. D/A converter output.
25
SPDO
Output
AVDD/2
SPINDLE control output pin. D/A converter output.
26
VVSS1
—
—
For use
by the
EFM
PLL
Circuit
by the
EFM
PLL
Circuit
Built-in VCO GND pin. This pin must always be connected to 0V.
27
PDOUT1
Output
UNSTABLE
Phase comparison output pin 1 to control built in VCO.
28
PDOUT0
Output
UNSTABLE
Phase comparison output pin 0 to control built in VCO.
29
PCKIST
Input
INPUT
Resistor connection pin to set current for PDOUT 0 and 1 output.
30
VVDD1
—
—
Built_in VCO power supply pin 1.
31*
DMUTEB
Output
L
DMUTEB output pin.
32
PUIN
Input/Output
INPUT
PUIN input pin. (built-in pull-up resistor)
33*
DEFECT
Output
L
DEFECT signal output pin.
34*
FSEQ
Output
L
Detected sync signal output. This signal is high when the sync signal
detected from the EFM signal and the internally generated sync signal
agree.
detected from the EFM signal and the internally generated sync signal
agree.
35*
C2F
Output
L
C2 error flag monitor output pin.
36
DVDD
—
—
Digital power supply pin.
37
DVSS
—
—
Digital GND pin. This pin must always be connected to 0V.
38
DVDD1.8
Output
H
Supply voltage connect to capacitor for digital circuit.
39
VDD3
—
—
Built-in VCO power supply pin 3.
40
VVSS3
—
—
Built-in VCO GND pin 3. This pin must always be connected to 0V.
41
DVDD
—
—
Digital power supply pin.
42
DVSS
—
—
Digital GND pin. This pin must always be connected to 0V.
43
CE
Input
INPUT
Micro-
Com-
puter
Inter-
face
Com-
puter
Inter-
face
Chip enable signal input pin.
44
CL
Input
INPUT
Data transfer clock input pin.
45
DI
Input
INPUT
Data input pin.
46
DO
Output
H
Data output pin. (TRI-State Output)
47
RESB
Input
—
Reset input pin for LSI. This pin must set to low briefly after power is
applied.
applied.
48
INTB0
Output
H
Interrupt signal output pin 0. (SERVO Section)
49
INTB1
Output
H
Interrupt signal output pin 1. (DECODER Section)
50
ICONT2
Input/Output
INPUT
General Purpose I/O pin 2 Controlled by command from the microproces-
sor. Any of these that are unused must be
either set up as input pin ports and connected
to 0V, or set up as output pin ports and left
open.
either set up as input pin ports and connected
to 0V, or set up as output pin ports and left
open.
CD-MPX880H
8 – 2
IC1 VHiLC78690E-1: CD Servo (LC78690E) (2/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal Name
Input/Output
Setting in Reset
Function
51
CONT1
Input/Output
INPUT
General Purpose I/O pin
1
1
Controlled by command from the microproces-
sor. Any of these that are unused must be
either set up as input pin ports and connected
to 0V, or set up as output pin ports and left
open.
sor. Any of these that are unused must be
either set up as input pin ports and connected
to 0V, or set up as output pin ports and left
open.
52
CONT0
Input/Output
INPUT
General Purpose I/O pin
0
0
53
TEST0
Input
L
Test input pin 1. This pin must always be connected to 0V.
54
STREQ
Input/Output
INPUT
Stream data request output pin.
55
STCK
Input/Output
INPUT
Stream data bit clock usage input pin.
56
STDATA
Input/Output
INPUT
Stream data input pin.
57
TEST1
Input
L
Test input pin 0. This pin must always be connected to 0V.
58*
DATA
Output
L
Left/Right clock output pin.
59*
DATACK
Output
L
Bit clock output pin.
60*
LRSY
Output
L
Left/Right channel data output pin.
61
VVDD2
—
—
For use by
the EFM
PLL Circuit
the EFM
PLL Circuit
Built-in VCO power supply pin 2.
62
VPREF2
Input
INPUT
Built-in VCO control oscillator range setting input pin.
63
VCOC2
Input
INPUT
Built-in VCO control voltage setting input pin.
64
VPDOUT2
Output
UNSTABLE
Built-in VCO control output pin 2.
65
VVSS2
—
—
Built-in VCO GND pin. This pin must always be connected to
0V.
0V.
66
DVDD1.8
Output
H
Supply voltage connect to condenser for digital circuit.
67
DVSS
—
—
Digital GND pin. This pin must always be connected to 0V.
68
DVDD
—
—
Digital power supply pin.
69*
DOUT
Output
Input
Digital output pin. EIAJ format.
70*
AMUTEB
Output
L
GAMUTEB output pin.
71
XVSS
—
—
Digital GND pin. This pin must always be connected to 0V.
72
XOUT
Output
OSCILLATING
Crystal
oscillator
oscillator
Connections for a 16.9344 MHZ oscillator element.
73
XIN
Input
OSCILLATING
74
XVDD
—
—
Digital power supply pin.
75
LCHO
Output
LRVDD/2
D/A con-
verter
verter
Left channel output supply pin.
76
LRVDD
—
—
LR channel power supply pin.
77
LRVSS
—
—
LR channel GND pin. This pin must always be connected to
0V.
0V.
78
RCHO
Output
LRVDD/2
Right channel input supply pin.
79
AVDD
—
—
Analog power supply pin.
80
SLCO
—
—
Slice level control output pin.
CD-MPX880H
8 – 3
IC1 VHiLC78690E-1: CD Servo (LC78690E)
1
EFMIN
RFOUT
LPF
PHLPF
AIN
CIN
BIN
DIN
FEC
RFMON
VREF
JITTC
EIN
FIN
TEC
TE
TEIN
AVSS
A
VDD
FD0
TD0
SLD0
SPD0
VVSS1
PDOUT1
PDOUT0
PCKIST
VVDD1
DMUTEB
PUIN
DEFECT
FSEQ
C2F
DV
D
D
D
VSS
VVDD3
VVSS3
D
V
DD1.8
LDD
LDS
2
3
3
4
5
6
7
8
9
7
8
9
10
11
12
13
14
12
13
14
15
16
16
17
18
19
18
19
20
21 22 23 24 25 26 27 28 29
31
30
32 33 34 35 36 37 38 39 40
60
59
58
58
57
56
55
54
53
52
51
54
53
52
51
50
49
48
47
49
48
47
46
45
45
44
43
42
43
42
41
80 79 78 77 76 75 74 73 72
70
71
69 68 67 66
63
64
65
62 61
DVDD
DVSS
CE
CL
DI
DO
RESB
INTB0
INTB1
CONT2
CONT1
CONT0
TEST0
STREQ
STCK
STDATA
TEST1
DATA
DATACK
LRSY
VVDD2
VPREF2
VCOC2
VPDOUT2
VVSS2
D
VDD1.8
D
VSS
DV
D
D
DOUT
AMUTEB
XVSS
XOUT
XIN
XVDD
LCH0
LR
VDD
LR
VSS
RCH0
AV
D
D
SLC0
LC78690E
VVDD2
VPREF2
VCOC2
VPDOUT2
VVSS2
D
VDD1.8
D
VSS
DV
D
D
DOUT
AMUTEB
XVSS
XOUT
XIN
XVDD
LCH0
LR
VDD
LR
VSS
RCH0
AV
D
D
SLC0
EFMIN
RFOUT
LPF
PHLPF
AIN
CIN
BIN
DIN
FEC
RFMON
VREF
JITTC
EIN
FIN
TEC
TE
TEIN
AVSS
LDD
LDS
AV
D
D
FD0
TD0
SLD0
SPD0
VVSS1
PDOUT1
PDOUT0
PCKIST
VVDD1
DMUTEB
PUIN
DEFECT
FSEQ
C2F
DV
D
D
D
VSS
VVDD3
VVSS3
D
V
DD1.8
DVDD
DVSS
CE
CL
DI
DO
RESB
INTB0
INTB1
CONT2
CONT1
CONT0
TEST0
STREQ
STCK
STDATA
TEST1
DATA
DATACK
LRSY
PLL2
AUDIO
I/F
Stream
I/F
Memory
1M
CPU I/F
&
PORT
CONTROL
DOUT
1bit DAC
8FS DIGITAL FILTER
DEEMPHASIS
CLOCK
GENERATOR
ATTENUATION CONTROL
INTERPOLATION MUTE
Audio FLT MUTE
MP3 & WMA
DECODER
Memory I/F
Synchronization
Detection
EFM
Demodulation
TEXT
ROM
DECODER
ERROR
CORRECTION
PLL3
SUBCODE DECODE
CD PLL
MONITOR
VREF
RF
SIGNAL
PROCESSOR
D/A
APC
JITTER
TES,HFL,
DEFECT
A/D
SERVO
CONTROL
SLICE LEVEL
CONTROL
LPF
Figure 8-1: BLOCK DIAGRAM OF IC
CD-MPX880H
8 – 4
IC2 VHILA6261//-1: Focus/Tracking/Spin/Sled Driver (LA6261)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
* Set power system GND to the minimum potential together with SGND.
* Short-circuit three pins of power system SVSS and PVCC1 externally before use.
Pin No.
Terminal Name
Function
1
VO3+
BTL Output pin (+) for channel 3.
2
VO3-
BTL Output pin (-) for channel 3.
3
VO2+
BTL Output pin (+) for channel 2.
4
VO2-
BTL Output pin (-) for channel 2.
5
VO1+
BTL Output pin (+) for channel 1.
6
VO1-
BTL Output pin (-) for channel 1.
7
PGND1
Power GND for channels 1,2,3 and 4 (BTL).
8
REGIN
Regulator pin (External PNP base).
9
PVCC1
Power for channels 1,2,3 and 4 (BTL). (SVCC short-crircuited)
10
REGOUT
Regulator pin (External PNP collector).
11
VIN1
Input pin for channel 1
12*
VIN1G
Input pin for channel 1 (for gain control)
13
VIN2
Input pin for channel 2
14*
VIN2G
Input pin for channel 2 (for gain control)
15
VIN3
Input pin for channel 3
16*
VIN3G
Input pin for channel 3 (for gain control)
17
VIN4
Input pin for channel 4
18
VIN4G
Input pin for channel 4 (for gain control)
19
FWD5
CH5 Output change pin (FWD). Logic input for bridge.
20
REV5
CH5 Output change pin (REV). Logic input for bridge.
21
VCONT5
Input pin for CH5 output voltage control
22
FWD6
CH6 Output change pin (FWD). Logic input for bridge.
23
REV6
CH6 Output change pin (REV). Logic input for bridge.
24
VCONT6
Input pin for CH5 output voltage control.
25
VREFIN
Reference voltage input pin.
26
SGND
Signal system GND
27
SVCC
Signal system power (PVCC1 short - circuited)
28
PVCC2
Power for channel 5 and 6 (H bridge).
29
MUTE
Input pin for BTL mute.
30
PGND2
Power GND for channels 5 and 6 (H bridge).
31
VO6+
H bridge Output pin (+) for channel 6.
32
VO6-
H bridge Output pin (-) for channel 6.
33
VO5+
H bridge Output pin (+) for channel 5.
34
VO5-
H bridge Output pin (-) for channel 5.
35
VO4+
BTL Output pin (+) for channel 4.
36
VO4-
BTL Output pin (-) for channel 4.
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