CD-E250 (serv.man18). Function table of IC — Sharp Audio Service Manual (repair manual)

Model
CD-E250 (serv.man18)
Pages
6
Size
66.54 KB
Type
PDF
Document
Service Manual
Brand
Device
Audio / System / Function table of IC
File
cd-e250-sm18.pdf
Date

View Sharp CD-E250 (serv.man18) Service Manual online

– 49 –
CD-E250E
CD-E550E
FUNCTION TABLE OF IC
IC401  VHiLC78646E-1: Servo/Signal Control (LC78646E) (1/2)
1
SLCO
Output
Control output.
2
SLCIST
Input
Resistor connection terminal for SLCO output current setting.
3
EFMIN
Input
RF signal input terminal.
4
RF
Output
RF signal monitor terminal.
5
RFVDD
Input
RF power terminal.
6
RFVSS
RF earth terminal. To be connected to 0 V.
7
FIN1
Input
A+C signal input terminal.
8
FIN2
Input
B+D signal input terminal.
9
TIN1
Input
E signal input terminal.
10
TIN2
Input
F signal input terminal.
11
VREF
Output
RFVDD/2
VREF voltage output terminal.
12
REF1
Input
Reference supply setting terminal.
13*
FE
Output
ZHI
FE signal monitor terminal.
14
TEC
Output
LPF capacitor connection terminal for TE signal.
15
TE
Output
ZHI
TE signal monitor terminal.
16*
RFMON
Output
ZHI
RF internal signal monitor terminal.
17
JITTC
Capacitor connection terminal for jitter detection.
18
ADAVDD
Input
Power terminal for servo A/D, D/A.
19
ADAVSS
Earth terminal for serve A/D, D/A. To be connected to 0 V.
20
TDO
Output
ADAVDD/2
Output terminal for tracking control. D/A output.
21
FDO
Output
ADAVDD/2
Output terminal for focus control. D/A output.
22
SPDO
Output
ADAVDD/2
Output terminal for spindle control. D/A output.
23
SLDO
Output
ADAVDD/2
Output terminal for sled control. D/A output.
24*
GPDAC
Output
ADAVDD/2
Servo D/A general-purpose output terminal.
25
CONT4
Input/Output
Input Mode
General-purpose I/O terminal 4.
26
CONT5
Input/Output
Input Mode
General-purpose I/O terminal 5.
27*
SBCK/CONT6
Input/Output
Input Mode
General-purpose I/O terminal 6 or
Subcode reading clock input terminal.
28
SBCK/FG
Input
Subcode reading clock input terminal/FG signal input terminal/external
emphasis setting terminal. Terminal functions are set by commands. When
not used, connect to 0 V.
29*
DEFECT
Output
L
Defect terminal.
30*
V/*P
Output
H
Auto switching monitor output terminal for rough servo phase control. “H”:
rough servo, “L”: phase servo.
31*
FSEQ
Output
L
Sync signal detection output terminal.
The status changes to “H” when the sync signal detected in EFM and the
sync signal of internal generation are identified.
32*
MONI1
Output
L
Internal signal monitor terminal 1.
33*
MONI2
Output
L
Internal signal monitor terminal 2.
34*
MONI3
Output
L
Internal signal monitor terminal 3.
35*
MONI4
Output
L
Internal signal monitor terminal 4.
36*
MONI5
Output
L
Internal signal monitor terminal 5.
37
VSS
Digital system earth terminal. To be connected to 0 V.
38
VDD
Input
Digital system power terminal.
39*
DOUT
Output
L
Digital OUT output terminal. (EIAJ format)
40
TEST
Input
L
Input terminal for test. To be connected to 0 V.
41
LVDD
Input
Power supply for Left channel.
42
LCHO
Output
LVDD/2
Left channel output.
43
LVSS
GND for Left channel. Must be connected to 0 V.
Pin No.
Function
Terminal Name Input/Output Setting in Reset
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Left channel
D/A converter
For slice level
control.
Controlled by commands from the
microcomputer. When not used, set
them as input terminals and connect
to 0 V, or set them as output
terminals and leave open.
CD-E250E
CD-E550E
– 50 –
44
RVSS
GND for Right channel. Must be connected to 0 V.
45
RCHO
Output
LVDD /2
Right channel output.
46
RVDD
Input
Power supply for Right channel.
47
XVDD
Input
Power supply for crystal oscillator.
48
XOUT
Output
Oscillator
Connected for the 33.8688 MHz crystal oscillator ciement.
49
XIN
Input
Oscillator
50
FSX/16MIN
Input/Output
Input
7.35 kHz Synchronization signal monitor port.
or Clock input port for Digital filter & D/A
51
XVSS
Crystal
GND for crystal oscillator. Must be connected to 0 V.
Oscillator
52*
C2F
Output
H
C2 FLAG monitor port.
53*
EFLG
Output
L
C1, C2 error corrected  monitor port.
54*
16MOUT
Output
Clock
16.9344 MHz output port.
55
ASLRCK
Input
Left/Right clock input port.
(If this port does not use, must be connect to 0 V.)
56
ASDACK
Input
Bit clock input port.
(If this port does not use, must be connect to 0 V.)
57
ASDFIN
Input
Left/Right channel data input port.
(If this port does not use, must be connect to 0 V.)
58*
LRCK
Output
L
Left/Right clock output port.
59*
BCK
Output
L
Digital data
Bit clock output port.
60*
DATA
Output
L
Left/Right channel data output port.
61
CE
Input
Chip enable signal input port.
62
CL
Input
Microcomputer
Data transfer clock input port.
63
DI
Input
Interface
Data input port.
64
DO
Output
(H)
Data output port. (N-ch. open drain output.)
65
*WRQ
Output
H
Interruption signal output.
66
*RES
Input
Chip reset signal input port.
This port must be set LOW after first applied power on.
67
DRF
Output
L
Focus detection output port.
68
VDD5
Input
Power supply for Microprocessor.
69
VSS
GND for digital circuit. Must be connected to 0 V.
70
CONT3
Input/Output
Input
General purpose port 3.
71
CONT2
Input/Output
Input
General purpose port 2.
72*
CONT1
Input/Output
Input
General purpose port 1.
73
PDO1
Output
Internal VCO control phase comparator output port 1.
74
PDO2
Output
Input
Internal VCO control phase comparator output port 2.
75
VVSS
GND for internal VCO. Must be connected to 0 V.
76
PCKIST
Input
PDO output current adjustment resistor connection port.
77
VVDD
Input
Power supply for internal VCO.
78
FR
Input
VCO frequency range adjustment port.
79
LDS
Input
LASER power detected signal input port.
80
LDD
Output
LASER power control signal output port.
IC401  VHiLC78646E-1: Servo/Signal Control (LC78646E) (2/2)
Pin No.
Function
Terminal Name Input/Output Setting in Reset
Right channel
D/A converter
Anti-shock
Controlled with serial data command from micro-
computer. When not used, General purpose input/
output terminal. Set it as the input terminal and open
it by connecting to 0 V, or set it as the output terminal
and open it.
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Be sure to supply the same potential to each power terminal. (VVDD, ADAVDD, VDD, LVDD, RVDD, XVDD)
Terminal witch is controlled by the power terminal (VDD5 V) for a microcomputer interface :
CE (61 pin), CL (62 pin), DI (63 pin), DO (64 pin), WRQ (65 pin), RES (66 pin), DRF (67 pin)
Crystal
Oscillator
PLL
– 51 –
CD-E250E
CD-E550E
Figure 51 BLOCK DIAGRAM OF IC
IC401  VHiLC78646E-1: Servo/Signal Control (LC78646E)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35 36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66 65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SLCO
SLCIST
EFMIN
RF
RFVDD
RFVSS
FIN1
FIN2
TIN1
TIN2
VREF
REF1
FE
TEC
TE
RFMON
JITTC
ADAVDD
ADAVSS
TDO
FDO
SPDO
SLDO
GPDAC
CONT4
CONT5
SBCK/CONT6
SBCK/FG
DEFECT
V/*P
FSEQ
MONI1
MONI2
MONI3
MONI4
MONI5
(3.3V)VSS
VDD
DOUT
TEST
LDD
LDS
FR
VVDD
PCKIST
VVSS
PD02
PD01
CONT1
CONT2
CONT3
VSS
VDD5
DRF
*RES
*WRQ
DO
DI
CL
CE
DATA
DATACK
LRSY
ASDFIN
ASDACK
ASLRCK
16MOUT
EFLG
C2F
XVSS
FSX/16MIN
XIN
XOUT
XVDD
RVDD
RCHO
RVSS
LVSS
LCHO
LVDD
LC78646E
+
+
+
+
MIX
LPF
LPF
LPF
TBAL
TBAL
RAM
LEVEL SET
EQ
SW
PH
BH
+
+
+
+
MNI
CONT
A/D
SERVO PROCESSOR
TRACK JUMP
AUTO ADJUST
JITTER
DETECT
1bit DAC
8FS
DIGITAL FILTER
GENERAL-PURPOSE
PORTS
COMMAND
INTERFACE
CLOCK
GENERATOR
CLV,CAV
CONTROL
PLL
VCEC
SLICE LEVEL
CONTROL
APC
S/H
D/A
SW
DRF
RUPTURE DEFECT
FRAME SYNC
DETECT,PROTECT INSERT,
EFM DECODE
VDD5V
SUBCODE DECODE CRC
MONITOR SIGNAL SELECTOR
RAM
ERROR
CORRECTION
AUDIO CD
C1-2,C2-2
AUDIO OUT
SERIAL
OUT
EXTERNAL
AUDIO IN
INTERPOLATION
MUTE
ATTENUATION
DEEMPHSIS
LPF
FIN1
FIN2
TIN1
TIN2
REF1
DEFECT
ADIN
ADAVDD
ADAVSS
JITTC
SLCO
EFMIN
SLCIST
PCK
PDO1
PDO2
FR
PCKIST
VVDD
VVSS
SBCK/FG
XIN
XOUT
16MOUT
XVDD
XVSS
*RES
*WRQ
CL
CE
DI
DO
VDD5V
CONT1, 2, 3
TEST
CONT4, 5,
SBCK/CONT6
LVDD
LVSS
LCHO
RCHO
RVDD
RVSS
ASDFIN
ASDACK
ASLRCK
DATA
DATACK
LRSY
DOUT
EFLG
C2F
FSX/16MIN
MONI1~5
VSS
VDD
V/*P
FSEQ
DRF
GPDAC
SPD0
SLD0
TD0
FD0
LDS
LDD
VREF
RFMON
RFVSS
RFVDD
RF
TEC
TE
FE
+
+
AGC
CD-E250E
CD-E550E
– 52 –
IC601  VHiLC75341M-1: Audio Processor (LC75341M)
Figure 52 BLOCK DIAGRAM OF IC
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
17
LVref
RVref
CONTROL
CIRCUIT
CONTROL
CIRCUIT
CONTROL
CIRCUIT
LOUT
LBASS
LIN
LSEL0
L4
L3
L2
L1
R1
R2
R3
R4
RSEL0
RIN
RTRE
LTRE
RBASS
ROUT
VREF
VDD
CLK
DI
CE
VSS
CCB
INTERFACE
CD
Tuner
Tape
Video
IC601  VHiLC75341M-1: Audio Processor (LC75341M)
Terminal Name
Pin No.
Function
1
DI
Serial data and clock input pin
for control.
2
CE
Chip enable pin.
Data written into an internal latch
in a timing of "H" to "L".
Each analog switch is activated.
Data transfer enabled at "H" level.
3
VSS
Ground pin.
4
LOUT
Bass band filter comprising
capacitor and resistor connection
pin and bass/treble output pin.
5
LBASS
Bass band filter comprisingcapacitor
and resistor connection pin.
6
LTRE
Treble band filter comprising
capacitor and resistor connection
pin.
7
LIN
Volume + equaliser output pin
8
LSEL0
Input selector output pin.
9-12
L4-1
Input signal pin.
Terminal Name
Pin No.
Function
13-16
R1-4
Input signal pin.
17
RSEL0
Input selector output pin.
18
RIN
Volume + equaliser output pin
19
RTRE
Treble band filter comprising
capacitor and resistor connection
pin.
20
RBASS
Bass band filter comprisingcapacitor
and resistor connection pin.
21
ROUT
Bass band filter comprising
capacitor and resistor connection
pin and bass/treble output pin.
22
VREF
0.5x VDD voltage generation block
for analog ground. Capacitor of
several 10
µ
F to be connected
between VREF and AWSS (VSS) as
a countermeasure against power
ripple.
23
VDD
Supply pin
24
CLK
Serial data and clock input pin
for control.
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