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– 37 –

47

DSLF

Input/Output

DSL loop filter terminal.

48

PLLF

Input/Output

PLL loop filter terminal.

49

VCOF

Input/Output

VCO loop filter terminal.

50

AVDD2

Input

Analog circuit power supply. (DSL, PLL and DA output sections for AD)

51

AVSS2

Input

Analog circuit GND. (DSL, PLL and DA output sections for AD)

52*

EFM, CK384

Output

· IOSEL=H: EFM signal output.
· IOSEL=L: X-tal system 16.9344 MHz clock output.
Signal processing system: 384fs output. (VCO clock for jitter-free operation)
(X-tal system or signal processing system can be selected by the command.)

53

PCK, DSLB

Output

PLL extraction clock output or DSL balance output. fPCK-4.3218 MHz

54

VCOF2

Input/Output

Loop filter terminal for digital servo 33.8688 MHz creation VCO.
X-tal 16.9344 MHz: external circuit is needed.

55*

SUBC

Output

Subcode serial output. CD-TEXT mode 1: TEXT data output.

56*

SBCK

Input

Subcode serial output clock input. CD-TEXT mode 1: TEXT data read clock input

57

VSS

Input

Oscillation circuit GND.

58

X1

Input

Oscillation circuit input terminal. f=16.9344 MHz, 33.8688 MHz

59

X2

Output

Oscillation circuit output terminal. f=16.9344 MHz, 33.8688 MHz

60

VDD

Input

Oscillation circuit power supply.

61*

BYTCK, TRVSTP

Output

IOSEL=H: byte clock signal output.
IOSEL=L: traverse STOP signal output. H: STOP Mode

62*

GIO1, /CLDCK

Output

Default: general purpose I/O port.
Command execution: terminal for subcode frame clock signal output. (fCLDCK=7.35 kHz)

63*

GIO2, FCLK

Output

Default: general purpose I/O port.
Command execution: crystal frame clock signal output. (fFCLK=7.35 kHz)

64*

IPFLAG

Output

Interpolation flag signal output. H: Interpolation

65*

FLAG

Output

Flag signal output.

66*

CLVS

Output

Output for spindle servo phase synchronization signal. H: CLV, L: Rough servo

67*

CRC

Output

Default: output for subcode CRC check results. H: OK, L: NG

68*

DEMPH

Output

Demphasis detection signal output. H: ON

69*

RESY, FLAG6

Output

IOSEL= H: resync signal RESY output for frame synchronization.
H: Synchronization, L: Synchronization lost
IOSEL=L: RAM address reset signal for error correct deinterleave.
FLAG 6 output L: Address reset

70

IOSEL

Input

Mode switch terminal.

71

/TEST

Input

Test terminal. Normal: H

72

AVDD1

Input

Analog circuit power supply. (Audio output section (for both Lch and Rch))

73

OUTL

Output

Lch audio output.

74

AVSS1

Input

Analog circuit GND. (Audio output section (for both Lch and Rch))

75

OUTR

Output

Rch audio output.

76

RSEL, GIO3

Input

Default: RF signal polarity specification terminal.
Brightness H: RESEL=H

Brightness L: RESEL=L

Command execution: general purpose I/O port.
RF signal polarity can be specified by command.
CD-TEXT mode 1 or 2: TEXT data read enabling signal (DQSY) output

77

CSEL

Input

Oscillation frequency specification terminal.
H: Oscillation frequency=33.8688 MHz L: Oscillation frequency=16.9344 MHz

78

PSEL

Input

IOSEL=H: test terminal. (Normal: L)
IOSEL=L: SRDATA input.

79

MSEL

Input

IOEL=H: SMCK terminal output, frequency switch terminal.
H: SMCK=8.4672 MHz

L: SMCK=4.2336 MHz

IOSEL=L: LRCK input
H: Lch data, L: Rch data
SMCK=4.2336 MHz fixed

80

SSEL

Input

IOSEL=H: switch terminal for SUBQ terminal output mode.
H: Q code buffer mode

L: CLDCK synchronization mode

IOSEL=L: BCLK input
Q code buffer mode fixed

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.

– 38 –

STAT

X1

X2

MSEL

CSEL

PMCK(PLAY)

GIO2(FCLK)

SMCK

BYTCK(TRVSTP)

VCOF

VCOF2

MDATA MCLK MLD

PSEL RSEL(GIO3) ARF DRF I

REF

DSLF PLLF2 PLLF EFM(CK384) PCK(DSLB) AV

DD2

AV

SS2

SUBQ SOCK(GIO0) SSEL

FLAG6(RESY)

IOSEL

DEMPH

SUBC

SBCK

GIO1(/CLDCK)

BLKCK

CRC

CLVS

SRDATAIN(PSEL) BCLKIN(SSEL) LRCKIN(MSEL)

V

DD

V

SS

DV

DD1

DV

SS1

/RST

/TEST

FE

RFENV

TE

TRCRS

BDO

VDET

/RFDET

OFT

SENSE

WVEL

LDON

/FLOCK /TLOCK

FBAL TBAL FOD TRD

TVD

VREF

TRV

KICK

TOFS

DMUTE

BCLK

SRDATA

LRCK

OUTR AV

DD1

AV

SS1

OUTL

IPFLAG

FLAG

PC

ECS

ECM

TIMING
GENERATOR
PITCH CONTROL

MICRO

COMPUTER

INTERFACE

SERVO

CPU

A/D CONVERTER

INPUT PORT

SERVO TIMING

GENERATOR

VCO

OUTPUT PORT

D/A

CONVERTER

INTER

POLATION

SOFT MUTING

DIGITAL

ATTENUATION

CLV

SERVO

DIGITAL

AUDIO

INTERFACE

16k

SRAM

PWM

(L)

PWM

(R)

1 BIT DAC

PWMLOGIC

8TIMES

OVER

SAMPLING

DIGITAL FILTER

DIGITAL

DEEMPHSIS

DSL • PLL VCO

SUBCODE

BUFFER

EFM    DEMODULATION

SYNC  INTERPOLATION

SUBCODE    DEMODULATION

CD-TEXT

BUFFER

CIRC ERROR CORRECTION

DEINTERLEAVE

-

+

-

+

TX

– 39 –

1
2
3

1G

2G

2G-7G

3G

4G

5G

6G

7G

8G

8G

(                      )

a

b

c

d

e

f

g

h

i

j

k

m

n

r

PIN NO.

1

2

3

4

5

6

7

8

9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8

CONNECTION

F

PIN NO.

CONNECTION

19

P1

F

20

P2

NP

21

P3

1G

22

P4

2G

23

P5

3G

24

P6

4G

25

P7

5G

26

P8

6G

27

P9

7G

28

P10

8G

29

P11

NC

30

P12

NC NC NC NC NC NC

31

P13

32

P14

33

NP

34

F

1G

P1

k

h

f

b
a
g

m

r

j

n

c

e
d

P2

P3

P4

P5

P6

P7

P8

P9

P10

P11

(Left)

P12

P13

P14

2G

3G

4G

5G

6G

7G

8G

1

2

3

(Right)

k

h

f

b
a
g

m

r

j

n

c

e
d

k
h

f

b

a

g

m

r

j

n

c

e
d

k
h

f

b
a

g

m

r

j

n
c

e

d

k

h

f

b
a

g

m

r

j

n

c

e

d

k
h

f

b

a

g

m

r

j

n
c

e

d

– 40 –

–– MEMO ––