Sharp CD-C470E (serv.man3) Service Manual ▷ View online
– 49 –
CD-C470H,C470E,C480H/CP-C470H,C470E,C480H
Function
Terminal Name Input/Output
49*
PW
Output
Output terminal of subcodes P, A, R, S, T, U and W.
50*
SFSY
Output
Output terminal of synchronous signal of subcode frame. It drops when subcode stands by.
51
SBCK
Input
Clock input terminal to read subcode. Schmit input (Connected to 0V when not used.)
52*
FSX
Output
Output terminal of synchronous signal of 7.35kHz divided from quartz oscillation.
53
WRQ
Output
Output terminal to stand by output of subcode Q.
54
RWC
Input
Input terminal of read/write. Schmit input.
55
SQOUT
Output
Output terminal of subcode Q.
56
COIN
Input
Command input terminal from microcomputer.
57
CQCK
Input
Clock input terminal to fetch command input, or pick up subcode from SQOUT. Schmit input
58
RES
Input
Reset input terminal of LC78622. When turning on power, set it at "L".
59*
TST11
Output
Output terminal for test. Used in the open state ("L" output as ordinary).
60*
16M
Output
Output terminal of 16.9344Hz.
61
4.2M
Output
Output terminal of 4.2336MHz.
62
TEST5
Input
Input terminal for test Pull-down resistor is integrated. Surely connected to 0V.
63
CS
Input
Chip selection input terminal. Pull-down resistor is integrated.
Connected to 0when not controlled.
Connected to 0when not controlled.
64
TEST1
Input
Input terminal for test Pull-down resistor is integrated. Surely connected to 0V.
Pin No.
Note: The same potential must be supplied to the power terminals (VDD, VVDD, LVDD, RVDD, XVDD).
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
DEFI
EFMIN
FSEQ
V/P
PW
SBCK
SBSY
SFSY
CS
WRQ
SQOUT
COIN
RWC
CQCK
HFL
TES
TOFF
JP-
JP+
RES
TGL
CONT1
CONT2
CONT3
CONT4
CONT5
EMPH
EFLG
16M
4.2M
XVss
FSX
XIN
XOUT
XV
DD
RVss
RV
DD
MUTER
RCHO
LCHO
MUTEL
LVss
LV
DD
(NC)
DOUT
C2F
EFMO
VV
DD
VVss
PDO
I SET
FR
PCK
TAI
TSTI1
TEST1
TEST2
TEST3
TEST4
TEST5
V
DD
Vss
CLV+
CLV-
Slice level
control
VCO colck oscillation
clock control
2 K x 8 b i t
R A M
RAM address
generator
Interpolation mute
Bilingual
Digital OUT
Digital
attenuator
X4 oversampling
digital filter
1 b i t D A C
L . P . F
XTAL system timing
generator
General-use port
Servo commander
É C O M
Interface
Subcode division
QCRC
C L V
Digital servo
Sync detection
EFM demodulation
Flag processing of C1/C2
error detection and correction
Figure 49 BLOCK DIAGRAM OF IC
IC2 VHiLC78623E-1:Servo/Signal Control(LC78623E) (1/2) (CD-C470H/C470E)
IC2 VHiLC78623D-1:Servo/Signal Control(LC78623D) (1/2) (CD-C480H)
IC2 VHiLC78623D-1:Servo/Signal Control(LC78623D) (1/2) (CD-C480H)
CD-C470H,C470E,C480H/CP-C470H,C470E,C480H
– 50 –
IC1 VHiLA9240M/-1:Servo Amp.,(LA9240M) (1/2)
1
FIN2
Connection pin for photodiode of pickup.
RF signal is generated through addition with FIN pin, and FE signal is generated through subtraction.
RF signal is generated through addition with FIN pin, and FE signal is generated through subtraction.
2
FIN1
Connection pin for photodiode of pickup.
3
E
Connection pin for photodiode of pickup. TE signal is generated through subtraction with F pin.
4
F
Connection pin for photodiode of pickup.
5
TB
Pin for input of DC component of TE signal.
6
TE-
Pin to connect gain setting resistor of TE signal to TE signal.
7
TE
TE signal output pin.
8
TESI
TES (Track error sense) comparator input pin. TE signal is band-passed and input.
9
SCI
Input pin for shock detection.
10
TH
Pin to set time constant of tracking gain.
11*
TA
TA amplifier output pin.
12
TD-
Pin to compose tracking phase compensation constant between TD and VR pins.
13
TD
Pin to set tracking phase compensation.
14
JP
Pin to set amplitude of tracking jump signal (kick pulse).
15
TO
Tracking control signal output pin.
16
FD
Focusing control signal output pin.
17
FD-
Pin to compose focusing phase compensation constant between FD and FA pins.
18
FA
Pin to compose focusing phase compensation constant between FD-/FA-pins.
19
FA-
Pin to compose focusing phase compensation constant between FA and FE pins.
20
FE
Output pin of FE signal.
21
FE-
Pin to connect gain setting resistor of FE signal across TE pin.
22
AGND
GND for analog signal.
23
SP
Single end output for CV+ and CV- pin input.
24
SPI
Spindle amplifier input.
25
SPG
Pin to connect gain setting resistor in the 12cm mode of spindle.
26
SP-
Pin to connect spindle phase compensation constant together with SPD pin.
27
SPD
Spindle control signal output pin.
28
SLEQ
Pin to connect thread phase compensation constant.
29
SLD
Thread control signal output pin.
30
SL-
Input pin of thread feed signal from micro computer.
31
SL+
Input pin of thread feed signal from micro computer.
32
JP-
Input pin of tracking jump signal from DSP.
33
JP+
Input pin of tracking jump signal from DSP.
34
TGL
Input pin of tracking gain control signal from DSP. TGL = Gain low at "H"
35
TOFF
Input pin of tracking off control signal from DSP. TOFF = Off at "H"
36
TES
Output pin of TES signal to DSP.
37
HFL
(HIGH FREQUENCY LEVEL) is used to judge whether main beam is positioned on the bit or on the mirror.
38
SLOF
Thread servo off control input pin.
39
CV-
Pin to input CLV error signal from DSP.
40
CV+
Pin to input CLV error signal from DSP.
41
RFSM
RF output pin.
42
RFS-
Pin to set gain of RF and set 3T compensation constant together with RFSM pin.
43
SLC
(SLICE LEVEL CONTROL) is the output pin to control of the level of the data slice with RF waveform DSP.
44
SLI
Input pin to control the level of data slice with DSP.
45
DGND
GND pin in the digital system.
46
FSC
Output pin for focus search smoothening capacitor.
47
TBC
(Tracking Balance Control) Pin to set EF balance variable range.
48*
NC
No connect.
49
DEF
Defect detection output pin of disk.
50
CLK
Reference clock input pin. 4.23MHz of DSP is input.
Pin No.
Port Name
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
– 51 –
CD-C470H,C470E,C480H/CP-C470H,C470E,C480H
IC1 VHiLA9240M/-1:Servo Amp.,(LA9240M) (2/2)
Pin No.
Port Name
Function
51
CL
Micro computer command clock input pin.
52
DAT
Micro computer command data input pin.
53
CE
Micro computer command chip enable input pin.
54
DRF
(DETECT RF) RF level detection output.
55
FSS
(Focus Serch Select) Pin to switch focus search mode. (
±
search/+ search for reference voltage)
56
VCC2
VCC pin for servo system and digital system.
57
REFI
Pin to connect pass control for reference voltage.
58
VR
Reference voltage output pin.
59
LF2
Pin to set defect detection time constant of disk.
60
PH1
Pin to connect capacitor for peak hold of RF signal.
61
BH1
Pin to connect capacitor for bottom hold of RF signal.
62
LDD
APC circuit output pin.
63
LDS
APC circuit output pin.
64
VCC1
RF system VCC pin.
Figure 51 BLOCK DIAGRAM OF IC
1
FIN2
FIN1
E
F
TB
TE-
TE
TESI
SCI
TH
TA
TD-
TD
JP
TO
FD
FD-
FA
FA-
FE
FE- AGND SP
SPI
SPG
SP-
SPD
SLEQ
SLD
SL- SL+
JP-
JP+
TGL
TOFF
TES
HFL
SLOF
CV-
CV+
RFSM
RFS-
SLC
SLI
DGND
FSC
TBC
NC
DEF
CLK
CL
DAT
CE
DRF
FSS
VCC2
REFI
VR
LP2
PH1
BH1
LDD
LDS
SLC
RF AMP
TE
F.SERVO & F.LOGIC
SPINDLE SERVO
SLED SERVO
VCC1
2
3
4
6
7
5
8
9
10
11
12
13
14
15
16
17
18
19
20
21
23
22
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
46
47
48
49
50
51
52
53
54
55
56
57
58
59
61
60
62
63
64
45
24
APC
RF DET
REF
VCA
VCA
INTER FACE
BAL
µ-COM
I/V
T.SERVO & T.LOGIC
CD-C470H,C470E,C480H/CP-C470H,C470E,C480H
– 52 –
IC601 RH-iX0171AWZZ:System Microcomputer (IX0171AW) (1/2)
1*
————
Output
—————
2
REC/PB
—
Record/Playback selection signal
3*
————
Output
—————
4
CD MUT
Output
CD MUT signal
5
CD RES
Output
CD DSP RESET signal
6
CD SL-
Output
Slide return signal
7
CD SL+
Output
Slide feed signal
8
VDD
—
Power connection terminal
9
CD CQCK
Output
CD IC control signal
10
CD COIN
Output
CD IC control signal
11
CD SQOUT
Input
CD IC control signal
12
CD WRQ
Input
CD IC control signal
13
CD RWC
Output
CD IC control signal
14
SCK
Input
Main
µ
COM (RH-iX0170AWZZ) control signal
15
SO
Output
Main
µ
COM (RH-iX0170AWZZ) control signal
16
SI
Input
Main
µ
COM (RH-iX0170AWZZ) control signal
17
RESET
Input
Main
µ
COM (RH-iX0170AWZZ) control signal
18
STROBE
Input
Main
µ
COM (RH-iX0170AWZZ) control signal
19
CD PU-IN SW
Input
Pickup position detection
20
AVSS
—
To be connected to GND
21
CD DRF
Input
CD RF level detection input
H: When RF level is H
22
T1 RUN
Input
Tape 1: Rotation pulse input
23
T2 RUN
Input
Tape 2: Rotation pulse input
24
SPEANA 5
Input
63Hz BPF spectrum analyzer input
25
SPEANA 4
Input
250Hz BPF spectrum analyzer input
26
SPEANA 3
Input
1kHz BPF spectrum analyzer input
27
SPEANA 2
Input
4kHz BPF spectrum analyzer input
28
SPEANA 1
Input
16kHz BPF spectrum analyzer input
29
AVDD
—
A/D converter analog positive power
30
AVREF
—
A/D converter reference power
31
TAPE CUM SW
Input
Tape mechanism cam SW input terminal
32*
————
—
No connected
33
VSS
—
To be connected to GND
34*
X1
—
Main clock terminal, not used
35*
X2
—
Main clock terminal, not used
36*
LINE MUT
Output
Line mute output, not used
37
SURROUND MUT
Output
Surround mute output
38
CENTER MUT
Output
Center SP output mute output
39
SYSTEM MUT
Output
System mute output
40
MIC
Input
Mic input terminal (for detection)
41
EN
Output
DOLBY PRO logic IC control signal
42
DATA
Output
DOLBY PRO logic IC control signal
43
CLK
Output
DOLBY PRO logic IC control signal
44
SP DET
Input
Speaker output error detection input
Occurrence of error: L
45
POWER
Output
Set power control output
Power ON: H
46*
RELAY
Output
Speaker output relay control output
Relay ON: H
47
TAPE TS CrO SW
Input
Tape mechanism 2 CrO
2
detection input
CrO
2
: H
48
VSS
Input
Digital GND terminal
49
TAPE F/R SPEED
Output
Tape feed/return
50
TAPE SOL
Output
Tape mechanism solenoid control output
Attraction: L
51
TAPE MOTOR
Output
Tape mechanism motor control output
Terminal Name
Pin No.
Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Function
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