DOWNLOAD Sharp CD-C421H (serv.man10) Service Manual ↓ Size: 101.4 KB | Pages: 9 in PDF or view online for FREE

Model
CD-C421H (serv.man10)
Pages
9
Size
101.4 KB
Type
PDF
Document
Service Manual
Brand
Device
Audio / System / IC function tables
File
cd-c421h-sm10.pdf
Date

Sharp CD-C421H (serv.man10) Service Manual ▷ View online

CD-C421H / C411H
– 42 –
1
DEFI
Input
Input terminal of defect detection signal (DEF). (Connected to OV when not used.)
2
TAI
Input
For PLL
Input terminal for test.  Pull-down resistor is integrated. Surely connected to 0V.
3
PDO
Output
Output terminal of phase comparison for external VCO control.
4
VVSS
Ground terminal for integrated VCO. Surely connected to 0V.
5
ISET
Input
Resistance connection terminal for current adjustment of PDO output.
6
VVDD
Power terminal for integrated VCO.
7
FR
Input
VCO frequency range adjustment.
8
VSS
Ground terminal of digital system. Surely connected to 0V.
9
EFMO
Output
For slice level control
EFM signal output terminal.
10
EFMIN
Input
EFM signal input terminal.
11
TEST2
Input
Input terminal for test.  Pull-down resistor is integrated. Surely connected to 0V.
12
CLV+
Outout
Output for disk motor control. 3 values can be output with the commands.
13
CLV-
Output
Output for disk motor control. 3 values can be output with the commands.
14
V/P
Output
Monitor output terminal for automatic switch of rough servo/phase control.
"H" for rough servo, and "L" for phase servo.
15
HLF
Intput
Input terminal of track detection signal. Schmit input.
16
TES
Input
Input terminal of tracking error signal. Schmit input.
17
TOFF
Output
Tracking OFF output terminal.
18
TGL
Output
Output terminal for switch of tracking gain  "L" increases the gain.
19
JP+
Output
Output for track jump control. 3 values can be output with the commands.
20
JP-
Output
Output for track jump control. 3 values can be output with the commands.
21*
PCK
Output
Clock monitor terminal for EFM data replay. 4,3218MHz as the phase clock.
22*
FSEQ
Output
Output terminal synchronous signal detection. "H" is output when synchronous signal detected
by EFM signal matches synchronous signal internally generated.
23
VDD
Power terminal of digital system.
24
CONT1
Input/Output
General purpose input/output terminal 1
25
CONT2
Input/Output
General purpose input/output terminal 2
26
CONT3
Input/Output
General purpose input/output terminal 3
27*
CONT4
Input/Output
General purpose input/output terminal 4
28*
CONT5
Input/Output
General purpose input/output terminal 5
29*
EMPH
Output
Difference monitor terminal  At "H", deemphasis disk is being replayed.
30*
C2F
Output
C2 flag output terminal.
31*
DOUT
Output
Output terminal of digital OUTPUT.   (EIAJ format)
32
TEST3
Input
Input terminal for test. Pull-down resistor is integrated. Surely connected to 0V.
33
TEST4
Input
Input terminal for test. Pull-down resistor is integrated. Surely connected to 0V.
34
N.C.
Terminal not used. Open during operation.
35*
MUTEL
Output
L channel  1 bit DAC
Mute output terminal for L channel.
36
LVDD
Power terminal for L channel.
37
LCHO
Output
L channel output terminal.
38
LVSS
Ground terminal for L channel   Surely connected to 0V.
39
RVSS
R channel  1 bit DAC
Ground terminal for R channel   Surely connected to 0V.
40
RCHO
Output
R channel output terminal.
41
RVDD
Power terminal for R channel.
42*
MUTER
Output
Mute output terminal for R channel.
43
XVDD
Power terminal for quartz oscillation.
44
XOUT
Output
Ground terminal of 16.9344 MHz quartz oscillator.
45
XIN
Input
Ground terminal of 16.9344 MHz quartz oscillator.
46
XVSS
Ground terminal for quartz oscillation. Surely connected to 0V.
47*
SBSY
Output
Output terminal of synchronous signal of subcode block.
48*
EFLG
Output
Correction monitor terminal of C1, C2, single and double.
IC2  VHiLC78622K-1:Servo/Signal Control(LC78622K)  (1/2)
FUNCTION TABLE OF IC
Pin No.
Function
Terminal Name Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Controlled with serial data command
from micro computer.
When not used, set it as the input terminal and
open it by connecting to 0V, or set it as the output
terminal and open it.
– 43 –
CD-C421H / C411H
VHiLC78622K-1:Servo/Signal Control(LC78622K)  (2/2)
Function
Terminal Name Input/Output
49*
PW
Output
Output terminal of subcodes P, A, R, S, T, U and W.
50*
SFSY
Output
Output terminal of synchronous signal of subcode frame. It drops when subcode stands by.
51
SBCK
Input
Clock input terminal to read subcode. Schmit input (Connected to 0V when not used.)
52*
FSX
Output
Output terminal of synchronous signal of 7.35kHz divided from quartz oscillation.
53
WRQ
Output
Output terminal to stand by output of subcode Q.
54
RWC
Input
Input terminal of read/write. Schmit input.
55
SQOUT
Output
Output terminal of subcode Q.
56
COIN
Input
Command input terminal from microcomputer.
57
CQCK
Input
Clock input terminal to fetch command input, or pick up subcode from SQOUT. Schmit input
58
RES
Input
Reset input terminal of LC78622. When turning on power, set it at "L".
59*
TEST11
Output
Output terminal for test. Used in the open state ("L" output as ordinary).
60*
16M
Output
Output terminal of 16.9344Hz.
61
4.2M
Output
Output terminal of 4.2336MHz.
62
TEST5
Input
Input terminal for test   Pull-down resistor is integrated. Surely connected to 0V.
63
CS
Input
Chip selection input terminal.  Pull-down resistor is integrated.
Connected to 0when not controlled.
64
TEST1
Input
Input terminal for test   Pull-down resistor is integrated. Surely connected to 0V.
Pin No.
Note: The same potential must be supplied to the power terminals (VDD, VVDD, LVDD, RVDD, XVDD).
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
DEFI
EFMIN
FSEQ
V/P
PW
SBCK
SBSY
SFSY
CS
WRQ
SQOUT
COIN
RWC
CQCK
HLF
TES
TOFF
JP-
JP+
RES
TGL
CONT1
CONT2
CONT3
CONT4
CONT5
EMPH
EFLG
16M
4.2M
XVss
FSX
XIN
XOUT
XV
DD
RVss
RV
DD
MUTER
RCHO
LCHO
MUTEL
LVss
LV
DD
(NC)
DOUT
C2F
EFMO
VV
DD
VVss
PDO
I SET
FR
PCK
TAI
TSTI1
TEST1
TEST2
TEST3
TEST4
TEST5
V
DD
Vss
CLV+
CLV-
Slice level
control
VCO colck oscillation
clock control
2 K x 8 b i t
R A M
RAM address
generator
Interpolation mute
Bilingual
Digital OUT
Digital
attenuator
X4 oversampling 
digital filter
1 b i t D A C
L . P . F
XTAL system timing 
generator
General-use port
Servo commander
µ
C O M
Interface
Subcode division
QCRC
C L V
Digital servo
Sync detection
EFM demodulation
Flag processing of C1/C2
error detection and correction
Figure 43 BLOCK DIAGRAM OF IC
CD-C421H / C411H
– 44 –
IC1 VHiLA9241M/-1:Servo Amp.(LA9241M) (1/2)
1
FIN2
Connection pin for photodiode of pickup.
RF signal is generated through addition with FIN pin, and FE signal is generated through subtraction.
2
FIN1
Connection pin for photodiode of pickup.
3
E
Connection pin for photodiode of pickup. TE signal is generated through subtraction with F pin.
4
F
Connection pin for photodiode of pickup.
5
TB
Pin for input of DC component of TE signal.
6
TE-
Pin to connect gain setting resistor of TE signal to TE signal.
7
TE
TE signal output pin.
8
TESI
TES (Track error sense) comparator input pin. TE signal is band-passed and input.
9
SCI
Input pin for shock detection.
10
TH
Pin to set time constant of tracking gain.
11*
TA
TA amplifier output pin.
12
TD-
Pin to compose tracking phase compensation constant between TD and VR pins.
13
TD
Pin to set tracking phase compensation.
14
JP
Pin to set amplitude of tracking jump signal (kick pulse).
15
TO
Tracking control signal output pin.
16
FD
Focusing control signal output pin.
17
FD-
Pin to compose focusing phase compensation constant between FD and FA pins.
18
FA
Pin to compose focusing phase compensation constant between FD-/FA-pins.
19
FA-
Pin to compose focusing phase compensation constant between FA and FE pins.
20
FE
Output pin of FE signal.
21
FE-
Pin to connect gain setting resistor of FE signal across TE pin.
22
AGND
GND for analog signal.
23
SP
Single and output for CV+ and CV- pin input.
24
SPI
Spindle amplifier input.
25
SPG
Pin to connect gain setting resistor in the 12cm mode of spindle.
26
SP-
Pin to connect spindle phase compensation constant together with SPD pin.
27
SPO
Spindle control signal output pin.
28
SLEO
Pin to connect thread phase compensation constant.
29
SLD
Thread control signal output pin.
30
SL-
Input pin of thread feed signal from micro computer.
31
SL+
Input pin of thread feed signal from micro computer.
32
JP-
Input pin of tracking jump signal from DSP.
33
JP+
Input pin of tracking jump signal from DSP.
34
TGL
Input pin of tracking gain control signal from DSP. TGL = Gain low at "H"
35
TOFF
Input pin of tracking off control signal from DSP. TOFF = Off at "H"
36
TES
 Output pin of TES signal to DSP.
37
HFL
(HIGH FREQUENCY LEVEL) is used to judge whether main beam is positioned on the bit or on the mirror.
38
SLOF
Thread servo off control input pin.
39
CV-
Pin to input CLV error signal from DSP.
40
CV+
Pin to input CLV error signal from DSP.
41
RFSM
RF output pin.
42
RFS-
Pin to set gain of RF and set 3T compensation constant together with RFSM pin.
43
SLC
(SLICE LEVEL CONTROL) is the output pin to control of the level of the data slice with RF waveform DSP.
44
SLI
Input pin to control the level of data slice with DSP.
45
DGND
GND pin in the digital system.
46
FSC
Output pin for focus search smoothening capacitor.
47
TBC
(Tracking Balance Control)  Pin to set EF balance variable range.
48*
NC
No connect.
49
DEF
Defect detection output pin of disk.
50
CLK
Reference clock input pin. 4.23MHz of DSP is input.
Pin No.
Port Name
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
– 45 –
CD-C421H / C411H
IC1 VHiLA9241M/-1:Servo Amp.(LA9241M) (2/2)
Pin No.
Port Name
Function
51
CL
Micro computer command clock input pin.
52
DAT
Micro computer command data input pin.
53
CE
Micro computer command chip enable input pin.
54
DRF
(DETECT RF) RF level detection output.
55
FSS
(Focus Serch Select)  Pin to switch focus search mode. (± search/+ search for reference voltage)
56
VCC2
VCC pin for servo system and digital system.
57
REFI
Pin to connect pass control for reference voltage.
58
VR
Reference voltage output pin.
59
LF2
Pin to set defect detection time constant of disk.
60
PHI
Pin to connect capacitor for peak hold of RF signal.
61
BHI
Pin to connect capacitor for bottom hold of RF signal.
62
LDD
APC circuit output pin.
63
LDS
APC circuit output pin.
64
VCC1
RF system VCC pin.
Figure 45 BLOCK DIAGRAM OF IC
1
FIN2
FIN1
E
F
TB
TE-
TE
TESI
SCI
TH
TA
TD-
TD
JP
TO
FD
FD-
FA
FA-
FE
FE- AGND SP
SPI
SPG
SP-
SPD
SLEQ
SLD
SL- SL+
JP-
JP+
TGL
TOFF
TES
HFL
SLOF
CV-
CV+
RFSM
RFS-
SLC
SLI
DGND
FSC
TBC
NC
DEF
CLK
CL
DAT
CE
DRF
FSS
VCC2
REFI
VR
LP2
PH1
BH1
LDD
LDS
SLC
RF AMP
TE
F.SERVO & F.LOGIC
SPINDLE SERVO
SLED SERVO
VCC1
2
3
4
6
7
5
8
9
10
11
12
13
14
15
16
17
18
19
20
21
23
22
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
46
47
48
49
50
51
52
53
54
55
56
57
58
59
61
60
62
63
64
45
24
APC
RF DET
REF
VCA
VCA
INTER FACE
BAL
µ-COM
I/V
T.SERVO & T.LOGIC
NC
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  • Here you can View online or download the Service Manual for the Sharp CD-C421H (serv.man10) in PDF for free, which will help you to disassemble, recover, fix and repair Sharp CD-C421H (serv.man10) System. Information contained in Sharp CD-C421H (serv.man10) Service Manual (repair manual) includes:
  • Disassembly, troubleshooting, maintenance, adjustment, installation and setup instructions.
  • Schematics, Circuit, Wiring and Block diagrams.
  • Printed wiring boards (PWB) and printed circuit boards (PCB).
  • Exploded View and Parts List.