Panasonic TX-32AR300 Service Manual ▷ View online
TX-32AR300
21
7.9.
Vesa Metal (BC)
1. Stick sponge at speaker area right & left.
2. Install vesa metal 2 pc into back cover.
2. Install vesa metal 2 pc into back cover.
No
Description
Qty
UOM
01
SPONGE
2
PC
02
VESA METAL
2
PC
TX-32AR300
22
7.10. Back Cover Installation
1. Install back cover.
2. Fix screws.
2. Fix screws.
No
Description
Qty
UOM
Remarks
01
BACK COVER
1
PC
02
SCREW (B7)
7
PC
6 ± 1 Kgf.cm
03
SCREW (AV5/CONT_BTN2))
7
PC
6 ± 1 Kgf.cm
04
SCREW (BC6)
6
PC
10 ± 2 Kgf.cm
TX-32AR300
23
8 Measurements and Adjustments
8.1.
Voltage chart of A-board
Set A-Board to a dummy set and check the satisfaction with the specified voltage as following table.
8.2.
Voltage chart of P-board
Set P-Board to a dummy load and check the satisfaction with the specified voltage as following table.
Power Supply Name
Measurement Point
Specification
PNL12V
TP4097
12.1 ± 0.8V
SUB3.3V
TP5400
3.32 ± 0.165V
SUB1.1V
TP8101
1.14 ± 0.07V
SUB1.5V
TP8100
1.52 ± 0.05V
SUB5V
TP5420
5.0 ± 0.25V
HDMI3.3V
TP8000
3.3 ± 0.16V
Output
Test Point
Specification
Operate
STBY
5.3V
TP7501
5.3 ± 0.20V
5.3 ± 0.20V
16V
TP7410/ TP7411/ TP7412
15.8 ± 0.5 V
-
24V
TP7511/ TP7512
24V ± 1.2 V
-
TX-32AR300
24
9 Block Diagram
9.1.
Main Block Diagram
S5/ S3.3
CPU BUS
XERWE0
XERWE0
XECS1
ERXW
ES0
XERWE0
XECS1
ERXW
ES0
AAR/DATA
CTRL
S12/S5
STB5/5VS
S9 REG
S9
(SD-Data-VCC)
CI POWER ON
>
S3.3
NAND
Support
Card
DTV_XRST
BOOTSWAP
XRST
XRSTSTM
XRST
XRSTSTM
ES0
ES1
ES2
ES1
ES2
ED[7:0]
2G - Function
VIErA-CAST Browser
EU MHP
UK BBC iPlayer
Latin GINGA MHP
VIErA-CAST Browser
EU MHP
UK BBC iPlayer
Latin GINGA MHP
< TV_SOS
AMP/HP MUTE
MONITOROUT MUTE
AMP/HP MUTE
MONITOROUT MUTE
Analog
ASIC
AN34043A
OVP
SOS
SOS
Safety
Circuit
Circuit
< MON_MUTE
< SP_HP_MUTE
< SP_HP_MUTE
STB3.3V/1.2V_REG
STB5V Reset IC (STM)
S9V_REG
S12V Reset IC (Peaks)
Audio MUTE
OCP/OVP/TV-SOS
HP_MUTE,EXT_MUTE
UHS-I_REG
TV_SOS
PWM
STB5V Reset IC (STM)
S9V_REG
S12V Reset IC (Peaks)
Audio MUTE
OCP/OVP/TV-SOS
HP_MUTE,EXT_MUTE
UHS-I_REG
TV_SOS
PWM
3.3/1.8
UHS-1
UHS-1
REG
S9-REG
< (SDVOLC)
PWM >
JTAG
HS1BCLKIN
HS1SYNCIN
HS1VALIN
HS1DIN0
HS1DIN1
HS1DIN2
HS1DIN3
HS1DIN4
HS1DIN5
HS1DIN6
HS1SYNCIN
HS1VALIN
HS1DIN0
HS1DIN1
HS1DIN2
HS1DIN3
HS1DIN4
HS1DIN5
HS1DIN6
TS-IN
S3.3 / TU1.8
DCDC
1.1V
S3.3
DMD IIC1 (IIC2)
S3.3
Only DVB-T2 models
SAT2.5 / SAT1.2
CI
ED[7:0]
Data Buffer
PCDOE
ERXW
ERXW
CI
Power
Circuit
Circuit
CI_POWER_ON
>
<
CI_OCP
LNB
Only SAT models
Flash
1G
XNFCE,XNFW
P
NFCLE,NFALE
XNFWE,XNFR
E
NANDRYBY
NFD[7:0]
P
NFCLE,NFALE
XNFWE,XNFR
E
NANDRYBY
NFD[7:0]
ED[
䋷
䋷:0]
Trans Port Decoder
CPUBUS
NAND-IF
Cross Stream Switch
Latin GINGA MHP
Back Light
INVERTER
or
LED Driver
BL_ON >
BL_SOS <
BL_SOS <
S12
Peaks
DCDC
DCDC
䋨VM䋩
S1.1
S1.5
S3.3
STB3.3
STB1.2
STB1.2
STB_XRST
DCDC_EN
DTV_XRST >
SW_OFF_DET >
XRST
POWER_DET
PWMA
PWM >
JTAG
AFB
S12
Peaks
DCDC
DCDC
HS1DIN6
HS1DIN7
HS1DIN8
HS1DIN7
HS1DIN8
Terrestrial
or
Terrestrial / Satellite
TUNER
IF_AGC1
1stLow_IF
䇮IFAGC
DMD_IIC0
Low-IF2
< FE_XRST
䋾
DVB-T2
Demod.
Demod.
IF_AGC2
Low-IF1
2ndLow_IF,IFAGC
CXD2837
< FE_XRST
䋾
DMD_IIC1 (IIC2)
DMD_IIC1 (IIC2)
PCOE
PCWE
PCIORD
PCIOWR
PCRESET
PCCE1
PCWE
PCIORD
PCIOWR
PCRESET
PCCE1
CI-IF
PCWAIT
PCCD1
PCCD2
PCREADY
PCCD1
PCCD2
PCREADY
CI-IF
(5V Tolerant)
(5V Tolerant)
TS-IN
TS-OUT
(5V Tole)
(5V Tole)
Panel
DMD
P-IIC2 (For DMD only)
ADC
DTV Decoder
SIF Decoder
IPR INS
Analog Video
Processor
Video
Format
Processor
VIF Decoder
IIC
DMD-IIC0
DMD-IIC1
DMD-IIC1
Peaks
sLD8
/9'67[
PLQL/9'67[
Tc
o
o
n
LVDS
HD : (DATA 4pairs / CLK 1pair) single8bit
FHD: (DATA 4pairs / CLK 1pair) dual8bit
VIO
R1, G1, B1, V1
Vout
Lin1,Rin1
Lout,Rout
Terrestrial
Satellite
< FE_SAT_RST
䋾
USB
S5
USB
USB*VBUS >
< USB*OC
< USB*OC
S5
USB Memory
86%,)
DSP
''5,)
S1.5
DDR3+(1333)
DDR3+(1333)
x16
1G
DDR3
AIO
V-SW
A-SW
DDR3+(1333)
DDR3+(1333)
x16
1G
S1.5
LIN2, RIN2
Head
HP1_L/R
HP_DET
FB,SLOW,QLINK
Y2,Pb2,Pr2/V2
R3, G3, B3, H,V
I2S
SW
SW
A-Chip
A-D Chip
Internal BUS
S5
᧤SRUW᧥
D-Chip
IIC
P-IIC0
P-IIC1
P-IIC1
Serial
P-Serial0
P-Serial1
P-Serial1
DMD IIC
DMD_IIC0
DMD_IIC1
DMD_IIC1
LAN
(7+(5
3+<
6',)
SD CARD
SOUND_VCC
PWM
AMP
LV4923V
Head
Phone
Phone
ALRCKO
ASDOUT0
ABCKO
ASMCK
ASDOUT0
ABCKO
ASMCK
AMP
PWM
SPDIF
SW
IIC
STM
P-UART0
P-UART2
P-UART2
EEP
S3.3
EEP
EEPROM_WP
P-IIC
For Peaks
HDMI
Rx
Optical OUT
OPT
DDC* > STM, Peaks
HPD* < STM
HDMI_5V_DET* > STM
HDMI_5V_DET* > STM
HDMI1
HDMI2
Rx*
Rx*
IECOUT
ARCOUT
CLK
GEN
GEN
STB3.3
STB1.2
STB1.2
STM-IIC
Serial
STM-Serial0
STM-Serial1
STM-Serial1
25MHz
< KEY1
POWER KEY
CONTROL PANEL KEY
MUX
x3
<
KEY3
DDC* > STM, Peaks
HPD* < STM
HDMI_5V_DET* > STM
HDMI_5V_DET* > STM
No use 24/19XM6
Power SW
USB Memory
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