Panasonic KX-TCD961EB Service Manual ▷ View online
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KX-TCD961EB
1. THE BASE-BAND SECTION (SEE BLOCK DIAGRAM Fig. 30)
1.1 INTRODUCTION
The base-band section consists of a base-band integrated circuit (BBIC), a Flash PROM, an EEPROM, an LCD
Display, a Microphone, an Earpiece, and power supply/battery management circuits.
1.2 THE BASE-BAND INTEGRATED CIRCUIT (BBIC)
The National SC14404 BBIC (IC1) is a CMOS device designed to handle all the audio, signal and data processing
needed in a DECT handset. It contains two microprocessors - one general purpose - while the other “burst mode
controller” takes care of DECT specific physical layer and radio section control.
The BBIC also contains the ADPCM transcoders, a low power 14 bit codec (ADC/DAC), various other ADC’s, DAC’s
and timers, a UART for data communication with RF unit, a gaussian filter for the DECT GFSK modulation method,
clock and data recovery circuits, a clock oscillator circuit, a battery management circuit, and a pair of gain
controllable amplifiers for the microphone and earpiece.
Fig.31
+3V +3V
Circuit Diagram
CIRCUIT OPERATION (HANDSET)
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1.3 FLASH PROM (SEE Fig. 31)
The 2 Mbit Flash PROM IC2 contains the operational firmware for the BBIC’s general purpose microprocessor. It is
interfaced to the BBIC using address lines AD0 to AD17, data lines DAB0 to DAB7, and the chip select (IC1 pin 84),
read (IC1 pin 86), and write (IC1 pin 93) control lines.
1.4 EEPROM (SEE Fig. 31)
The electrically erasable PROM IC3 is used to store all the temporary operating parameters for the handset
(see EEPROM LAYOUT page 69). It used a two-line serial data interface with the BBIC(TP82), with bi-directional data
on IC3 pin 5, and a 45 kHz clock on pin 6 (TP83).
1.5 LCD DISPLAY, AND DISPLAY DRIVER (SEE Fig. 32)
The LCD display also receives data via a serial interface. Serial data is sent to LCD display on pin 3 (TP70).
The RS signal (pin 1, TP67) is used by the BBIC to send either commands or data.
Fig. 32
Circuit Diagram
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Fig. 33
1.6 AUDIO PATH - TX AUDIO (SEE Fig. 33)
Balanced audio from the microphone (TP40 and TP41) enters the BBIC at pins 61 and 63. A balanced bias voltage for
the (“electret” type) microphone is supplied by the BBIC from pins 60 and 64 via R31 and R32. This supply is
de-coupled by R22, R27, C21, C28, and C22. RF de-coupling of the microphone signal is provided by R27, C25, R28,
C26, R24, R25, and C20.
The microphone audio signals are coupled to the BBIC via C22 and C23, which provide some high pass filtering.
In the BBIC audio passes through the gain-controlled microphone amplifier, into the ADC part of the codec, where it is
sampled and turned into digital data. The burst mode controller then processes this raw data (called the B-field)
performing encryption and scrambling, adding the various other fields that go together to produce the GAP standard
DECT frame, assigning to a time slot and channel etc. The data then passes through the gaussian filter to emerge on
pin 20 as TRADAT.
1.7 AUDIO PATH - RX AUDIO (SEE Fig. 33)
Audio from the receiver RECDAT (TP54) enters the BBIC on pin 18 and passes through the clock recovery circuit. The
burst mode controller separates out the B-field data, and performs de-encryption and de-scrambling as required. It
then goes to the DAC part of the codec where data is turned back into analogue audio. The audio signal is
amplified by the gain-controlled earpiece amplifier, and balanced audio is output on pins 65 and 66, and fed to the
earpiece (TP31 and TP32). The leads feeding the earpiece are RF de-coupled by C15 to R22, C17, C16, R23, and
C18. C19 provides low pass filtering.
Circuit Diagram
DAC
CODEC
ADC
B.M.C.
GAUSS FILTER
RSSI ADC
CLOCK/DATA
RECOVERY
RECOVERY
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1.8 CLOCK GENERATION (SEE Fig. 33)
A single clock generator in the BBIC uses an external crystal X1 to derive all clock frequencies used in the handset.
The crystal is tuned to the exact frequency of 10.368 MHz during manufacture by feeding a DC voltage from an
internal DAC (from pin 12) to the varicap diode D12 (TP25). The RFCLK output (pin 10, TP56) is a buffered clock
signal at 10.368 MHz for the Frequency Synthesizer, that is only active during the PLL lock period (see section 1.3).
The basic data rate for TX-DATA and RX-DATA is 1.152 Mbits/s, which is divided by 9. The data rate for the serial
interface to the phase-lock-loop is also 1.152 Mbits/s.
1.9 KEYBOARD (SEE Fig. 34)
The keyboard “On” button is connected directly to pin 41 of the BBIC (TP10). When pressed it turns the handset on
and off (must be held for off). All other keys are connected in a row/column matrix. They are scanned in six rows using
scan pulses (only active when keys are pressed) from IC1 pins 28 to 33. The four key matrix columns are input to the
BBIC on pins 31 to 34.
Fig. 34
Circuit Diagram
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