Panasonic KX-TCD953RUB (serv.man2) Service Manual ▷ View online
5 BLOCK DIAGRAM BASEBAND SECTION AND LINE INTERFACE (BASE UNIT)
KX
-T
CD9
53RU
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6 CIRCUIT OPERATION (BASE UNIT)
6.1. THE BASE-BAND SECTION (SEE BLOCK DIAGRAM Fig. 18)
6.1.1. INTRODUCTION
The base-band section consists of a base-band integrated circuit (BBIC), a Flash PROM and an EEPROM.
6.1.2. THE BASE-BAND INTEGRATED CIRCUIT (BBIC)
The PQVINSC14424 (IC101) is a CMOS device designed to handle all the audio, signal and data processing needed in a DECT
base unit. It contains a "burst mode controller” microprocessor which takes care of DECT specific physical layer and radio section
control. It also contains two ADPCM transcoders, a low power 14 bit codec (ADC/DAC), various other ADC´s, DAC´s and timers,
a gaussian filter for the DECT GFSK modulation method, clock and data recovery circuits, a clock oscillator circuit, a DTMF
generator (DSP), an echo suppression circuit (DSP), and a pair of gain controllable audio amplifiers for line input and line output
and a general purpose microcontroller.
The IC101 interfaces to its external PROM (IC102) via a data/address/control bus. It connects to the EEPROM via a serial
interface, and a second serial interface is used during manufacture and service to connect to an external computer.
base unit. It contains a "burst mode controller” microprocessor which takes care of DECT specific physical layer and radio section
control. It also contains two ADPCM transcoders, a low power 14 bit codec (ADC/DAC), various other ADC´s, DAC´s and timers,
a gaussian filter for the DECT GFSK modulation method, clock and data recovery circuits, a clock oscillator circuit, a DTMF
generator (DSP), an echo suppression circuit (DSP), and a pair of gain controllable audio amplifiers for line input and line output
and a general purpose microcontroller.
The IC101 interfaces to its external PROM (IC102) via a data/address/control bus. It connects to the EEPROM via a serial
interface, and a second serial interface is used during manufacture and service to connect to an external computer.
6.1.3. FLASH PROM (SEE Fig. 19)
The 2 Mbit (IC102) Flash PROM contains the operational firmware for the microcontroller. It is interfaced to the
data/address/control bus using address lines A0 to A16, data lines D0 to D7, and chip select (pin 30), output enable (pin 32), and
write (pin 7).
data/address/control bus using address lines A0 to A16, data lines D0 to D7, and chip select (pin 30), output enable (pin 32), and
write (pin 7).
6.1.4. EEPROM (SEE Fig. 19)
The electrically erasable PROM PQVINM4C32L (IC103) is used to store all the temporary operating parameters for the base (see
EEPROM LAYOUT). It uses a two-line serial data interface with the BBIC, with bi-directional data on pin 5 (TP156), and clock on
pin 6 (TP155).
EEPROM LAYOUT). It uses a two-line serial data interface with the BBIC, with bi-directional data on pin 5 (TP156), and clock on
pin 6 (TP155).
6.1.5. CLOCK GENERATION (SEE Fig. 19)
A single clock generator in the BBIC uses an external crystal X101 to derive all clock frequencies used in the base. The crystal is
tuned to the exact frequency of 10.368 MHz during manufacture by feeding a DC voltage from a DAC in the microcontroller (from
pin 14 of IC101) to the varicap diode D104 (TP112).
The BBIC provides buffered clock signals RFCLK (pin 11, TP157) at 10.368 MHZ for the Frequency Synthesizer, which is only
active during the PLL lock period. Other clock is SCLK on pin 1 (3.456MHz). The basic data rate for TRADAT and RECDAT is
1.152 Mbits/s, which is 10.368 MHs divided by 9. The data rate for the serial link to the phase lock loop is 45.5 kbits/sec.
tuned to the exact frequency of 10.368 MHz during manufacture by feeding a DC voltage from a DAC in the microcontroller (from
pin 14 of IC101) to the varicap diode D104 (TP112).
The BBIC provides buffered clock signals RFCLK (pin 11, TP157) at 10.368 MHZ for the Frequency Synthesizer, which is only
active during the PLL lock period. Other clock is SCLK on pin 1 (3.456MHz). The basic data rate for TRADAT and RECDAT is
1.152 Mbits/s, which is 10.368 MHs divided by 9. The data rate for the serial link to the phase lock loop is 45.5 kbits/sec.
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KX-TCD953RUB
Circuit Diagram
Fig19
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KX-TCD953RUB
6.1.6. FACTORY SERIAL PORT (SEE Fig. 19)
In order to communicate with the handset during manufacture and servicing (using a PC) a serial data link has been provided.
Serial data input/output is provided on J102 (TP151), and a ground is provided on J103. The bi-directional serial data line is split
into two at IC101 pin 27 (input) and pin 26 (output). Data rate is 9600 baud. D105 provides ESD protection, and R117 and C146
provide RF de-coupling.
Serial data input/output is provided on J102 (TP151), and a ground is provided on J103. The bi-directional serial data line is split
into two at IC101 pin 27 (input) and pin 26 (output). Data rate is 9600 baud. D105 provides ESD protection, and R117 and C146
provide RF de-coupling.
6.1.7. AUDIO PATH-RX AUDIO-LINE INPUT (SEE Fig. 20)
Audio from the Line Interface TXAF (TP123) enters the BBIC on pin 58. R111 and C113 are to balance the line input amplifier, into
the ADC part of the codec, where it is sampled and turned into digital data. The burst mode controller then processes this raw data
(called the B-field) performing encryption and scrambling, adding the various other fields that go together to produce the GAP
standard DECT frame, assigning to a time slot and channel etc. The data then passes through the gaussian filter to emerge on pin
22 as TRADAT, (TP132).
the ADC part of the codec, where it is sampled and turned into digital data. The burst mode controller then processes this raw data
(called the B-field) performing encryption and scrambling, adding the various other fields that go together to produce the GAP
standard DECT frame, assigning to a time slot and channel etc. The data then passes through the gaussian filter to emerge on pin
22 as TRADAT, (TP132).
6.1.8. AUDIO PATH - TX AUDIO - LINE OUTPUT (SEE Fig. 20)
Audio from the receiver RECDAT enters the BBIC on pin 20 and passes through the clock recovery circuit. The burst mode
controller separates out the B-field data, and performs de-encryption and de-scrambling as required. It then goes to the DAC part
of the codec where data is turned back into analogue audio. The audio signal is amplified by the gain-controlled line output
amplifier, and balanced audio is output on pin 63, and fed as RXAF (TP120) to the Line Interface.
controller separates out the B-field data, and performs de-encryption and de-scrambling as required. It then goes to the DAC part
of the codec where data is turned back into analogue audio. The audio signal is amplified by the gain-controlled line output
amplifier, and balanced audio is output on pin 63, and fed as RXAF (TP120) to the Line Interface.
Circuit Diagram
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KX-TCD953RUB
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