Panasonic KX-AT7730RU (serv.man2) Service Manual ▷ View online
7
KX-AT7730 Series
4.2.
Circuit Operations
4.2.1.
KEY INPUT CONTROL CIRCUIT
Sequential input information is executed by dynamic scanning.
The ports P3_1, P3_6, P8_4-6, P8_1 of IC1 are brought to high status consecutively.
If a key is pressed, the key-in information input is executed by ports P2_1-7.
The ports P3_1, P3_6, P8_4-6, P8_1 of IC1 are brought to high status consecutively.
If a key is pressed, the key-in information input is executed by ports P2_1-7.
Circuit Diagram
SW34
4
SW19
CO6
SW27
9
SW13
CO10
D32
B8
Q114
4
3
5
SW29
CONF
B7
SW20
CO5
SW33
*
B6
D31
SW50
SW32
STORE
Q113
1
6
2
B5
SW24
CO3
SW14
CO9
B4
SW49
SW35
M.W
SW46
6
RA2
SW26
CO1
SW47
E6
SW16
1
SW15
7
E5
DG
D34
SW36
PAUSE
SW39
0
SW25
CO2
D33
SW37
FLASH
SW41
REDIAL
SW18
CO7
SW22
2
SW44
ICM
SW21
8
SW40
5
SW48
SW52
HOOK
SW28
3
B3
Q112
4
3
5
SW45
#
SW12
CO11
B2
IC1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SW43
SP-PHONE
SW30
FWD/DND
AG
AG
B1
SW17
CO8
SW23
CO4
Q111
1
6
2
SW38
TRANSFER
SW31
MUTE
SW51
PROGRAM
SW11
CO12
E1
E4
E2
E3
K[7]
K[3]
K[5]
K[2]
K[6]
K[0]
K[4]
K[1]
K[2]
K[1]
K[5]
K[0]
K[6]
K[4]
K[3]
K[7]
C[5]
C[4]
C[3]
C[2]
C[1]
C[0]
SW42
HOLD
P3_5
P3_4
P3_3/*INT3
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P3_6
P3_1
P8_6
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P6_7
P6_6/TXD2
P6_5/CLK2
P4_5
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
P0_
7/DA1
P0_
6/DA0
P0_5
T_CONT1
P0_3
P0_2
P0_1
P0_0
P6_4
P6_3
P6_2
P6_1
P6_0
P5_7
P5_6
P3_2
P3_0
P4_2/VREF
MODE
HS_MUTE
P4_4/XCOUT
*RESET
P4_7/XOUT
VSS/AVSS
P4_6/XIN
VCC/AVCC
P5_4
P5_3
P5_2
P5_1
P5_0
P3_7
8
KX-AT7730 Series
4.2.2.
LED CIRCUIT
Circuit Operation:
The LED executes dynamic lighting for the status indicators, and control is executed by the output ports P3_1, P3_6, P8_5-6, P4_5,
P1_1-7.
P1_1-7.
Circuit Diagram
E4
Q114
4
3
5
Q108
1
4
3
2
5
D27
CO10
R139
D18
CO1
Q113
1
6
2
R137
R131
D12
ICM
RA2
D23
CO6
D5V
DG
D17
STORE
D22
CO5
R133
E1
A1
E2
R134
E3
D16
MUTE
R132
D19
CO2
A6
D28
CO11
D13
SP-PHONE
CN4
1
2
Q105
1
4
3
2
5
A5
D25
CO8
A4
D24
CO7
A3
D15
FWD/DND
A2
D26
CO9
D29
CO12
3
4
1
2
D14
CONF
R138
Q112
4
3
5
D20
CO3
D11
M.W
IC1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Q106
1
4
3
2
5
R136
R140
A9
Q111
1
6
2
Q107
1
4
3
2
5
D21
CO4
A8
CN5
1
2
A7
R135
L[7]
L[6]
L[2]
C[2]
L[3]
L[3]
L[4]
L[5]
L[4]
L[6]
L[7]
L[5]
C[1]
L[0]
L[1]
C[0]
L[0]
C[3]
L[1]
L[2]
G
G
G
R
G
R
G
R
G
R
R
R
R
G
G
R
G
R
G
G
G
R
R
R
P3_5
P3_4
P3_3/*INT3
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P3_6
P3_1
P8_6
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P6_7
P6_6/TXD2
P6_5/CLK2
P4_5
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
P0_
7/DA1
P0_
6/DA0
P0_5
T_CONT1
P0_3
P0_2
P0_1
P0_0
P6_4
P6_3
P6_2
P6_1
P6_0
P5_7
P5_6
P3_2
P3_0
P4_2/VREF
MODE
HS_MUTE
P4_4/XCOUT
*RESET
P4_7/XOUT
VSS/AVSS
P4_6/XIN
VCC/AVCC
P5_4
P5_3
P5_2
P5_1
P5_0
P3_7
9
KX-AT7730 Series
4.2.3.
DATA COMMUNICATION CIRCUIT
1) Reception
The data from the PBX is received via the H and L lines along the path shown below.
The data from the PBX is received via the H and L lines along the path shown below.
H, L Line
→ D2 → T2 → R106 → Q102 → IC9 → IC1 Pin 19
2) Transmission
The data to the proprietary telephone is transmitted along the following path.
The data to the proprietary telephone is transmitted along the following path.
IC1 Pin 16
→ Q101 → T2 → D2 → H, L Line
DATA
INPUT
INPUT
DATA
OUTPUT
OUTPUT
(P3_3)
(P3_7)
Start Signal
(Max. 19 pulses)
(Max. 47 pulses)
Acknowledge Signal
Timing Chart
Circuit Diagram
IC1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DOUT
DOUT
DI_INT
DI_INT
P3_5
P3_4
P3_3/*INT3
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P3_6
P3_1
P8_6
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P6_7
P6_6/TXD2
P6_5/CLK2
P4_5
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
P0_
7/DA1
P0_
6/DA0
P0_5
T_CONT1
P0_3
P0_2
P0_1
P0_0
P6_4
P6_3
P6_2
P6_1
P6_0
P5_7
P5_6
P3_2
P3_0
P4_2/VREF
MODE
HS_MUTE
P4_4/XCOUT
*RESET
P4_7/XOUT
VSS/AVSS
P4_6/XIN
VCC/AVCC
P5_4
P5_3
P5_2
P5_1
P5_0
P3_7
D6
Q101
IC7
3
OUT
2
GND
1
VCC
D4
D5
D7
C103
C101
T2
1
2
4
5
6
7
10
9
8
R106
R108
R101
R102
R201
R103
R107
R105
R104
DG
D3.3V
D3.3V
DG
D3.3V
DG
DG
D3.3V
+6V
D5V
D3.3V
DG
A5V
DG
DG
AG
AG
DG
DG2
D3.3V
DG
+6V
D5V
V1
J4
J1
IC9
1
NC
2
A
4
Y
5
VCC
3
GND
R300
NC
D3.3V
R301
NC
R302
NC
R303
NC
IC11
1 CE
2 GND
3
VOUT
4
VDD
C205
C102
NC
Q102
DG
Q110
( )
NC
C104
C204
C210
D2
4
1
3
2
C203
D40
C215
C206
10
KX-AT7730 Series
4.2.4.
TONE GENERATION CIRCUIT
Function:
This circuit generates all system tones including COL, extension, busy, DTMF signals and key in confirmation tones during the
power failure mode and is comprised of IC1(DTMF Generator) and IC5 (Analog Switch).
Circuit Operation:
power failure mode and is comprised of IC1(DTMF Generator) and IC5 (Analog Switch).
Circuit Operation:
For an output of a single row tone, the row terminal and the each column terminals intersecting with it are required to be brought a
low state. For a dual tone output, one row terminal and one column terminal are brought to low state.
low state. For a dual tone output, one row terminal and one column terminal are brought to low state.
CONDITION
IC1 pin52
IC5 SWA
IC1 pin53
IC5 SWB
IC1 pin54
IC5 SWC
IC1 pin55
IC5 SWD
Ringing
L
OFF
L
OFF
L
OFF
H
ON
Call Waiting
L
OFF
L
OFF
H
ON
L
OFF
Tone Dial (Handset)
H
ON
H
ON
L
OFF
L
OFF
Tone Dial (Speakerphone) H
ON
L
OFF
H
ON
L
OFF
Circuit Diagram
C28
R31
R30
C29
C84
C31
Q8
R84
IC1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R124
R123
A5V
T_CONT1
T_CONT3
T_CONT4
R81
C81
T_CONT2
T_CONT1
T_CONT2
T_CONT3
T_CONT4
C63
C61
AG
C66
AG
R80
CN3
1
+
2
-
C67
R85
AG
Parity Circuit Board 1
P3_5
P3_4
P3_3/*INT3
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P3_6
P3_1
P8_6
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P6_7
P6_6/TXD2
P6_5/CLK2
P4_5
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
P0_
7/DA1
P0_
6/DA0
P0_5
T_CONT1
P0_3
P0_2
P0_1
P0_0
P6_4
P6_3
P6_2
P6_1
P6_0
P5_7
P5_6
P3_2
P3_0
P4_2/VREF
MODE
HS_MUTE
P4_4/XCOUT
*RESET
P4_7/XOUT
VSS/AVSS
P4_6/XIN
VCC/AVCC
P5_4
P5_3
P5_2
P5_1
P5_0
P3_7
IC5
1
I/O1
2
O/I1
12
CONT4
13
CONT1
3
O/I2
14
VDD
4
I/O2
11
I/O4
5
CONT2
10
O/I4
6
CONT3
9
O/I3
7
VSS
8
I/O3
R82
R86
R87
C82
NC
AG
D3.3V
R88
AG
D3.3V
AG
R296
NC
AG
AG
C85
C86
IC8
1
IN/OUT
2
OUT/IN
3
GND
5
VCC
4
CONT
AG
R89
68k
D3.3V
R144
470
R90
470
AG
AG1
K1
K2
N1
N2
N3
N4
CN7-6
CN8-1
CN8-5
CN7-7
CN7-3
CN8-2
Q18
SW1
4
C
1
2
3
5
6
RING_OFF
CN8
CN7
C6
C7
R9
R10
R7
C5
NC
AG
R8
AG
T1
1
6
3
4
2
Q3
C4
C14
IC3
1
RR
2
RTX
3
TXI
4
TXO
5
TLI
23
XDC
24
VLC
25
ACF
26
RXO
27
RXI
6
TLO
7
RLI
8
RLO
9
MCI
10
MCO
12
CP2
13
XDI
14
SKG
18
*CS
19
SKI
20
VCC
21
VB
22
GND
15
SKO
16
V+
17
AGC
11
CP1
28
RRX
L4
R79
R78
+6V
AG
0
R61
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