Panasonic TH-42PY70FA / TH-42PY70PA / TH-42PZ70BA / TH-42PZ70EA Simplified Service Manual ▷ View online
3.1. Schematic Diagram Note
3 Schematic and Block Diagram
TH-42PY70FA / TH-42PY70PA / TH-42PZ70BA / TH-42PZ70EA
21
3.2. Main Block Diagram
DH
OSD
25
FULL HD
DH
DH5
D5
25
FPGA
DG
GP5P_1st
(CYCLONE)
DDR
CH0DATA
FAN CONTROL
LINE
CONTROL
S.R.
SUSTAIN
D36
*Plasma AI
POWER SW
R
S.R.
S.R.
Vda
Discharge
Control(SC)
Control(SC)
ASDIO
C2
S.R.
SWITCH
S.R.
SOS7
PULSE
P5V
RECTIFIER
C20
*H,V Snyc Control
AMP
+15V
SOS6
PA34
DG
P5V
MICOM
PROCESSOR
S.R.
AUDIO IN
AV SWITCH
D/A
EEPROM
POWER
+15V
END
STANDBY
SC2
GS52
D20
POWER LED
DG1
15V
+12V(s)
VOLTAGE
S.R.
G[9:0]
PRO.
S.R.
R[9:0]
C3
ADDRESS
HDMI_SPDIF
AV3 IN
AD/HDMI
Peaks-Lite 2
Data Driver
Control
Control
DTV_SDIN
VOLTAGE
VDA_75V
PLASMA AI PROCESSOR
S.R.
SCAN DRIVE
SENSOR
SD
PULSE
SU
DG
12
12
D35
D25
SS
DG
MAIN
MICOM
D34
FORMAT CONVERTER,
C11
+15V
(VE)
PA32
C1
SD CARD SLOT
S.R.
STB_PS
VOLTAGE
DATA DRIVER(LEFT)
G
SUSTAIN
DTV
S.R.
S.R.
FILTER
*CLK
Vda
POWER_SOS
RESET
SUSTAIN DRIVE
VDA_75V
S.R.
PROTECTION(SOS)
P
RECTIFIER
S.R.
PD1-M plus
VOLTAGE
WRITE PROTECT
5V
15V
SS23
DISPEN
DC/DC
3.3V
3.3V
P5V
+12V
PCLK/NCLK
S.R.
PROCESS
ERASE
POWER SUPPLY
SUS
+15V
D
S1
SOS7
TEMP
REMOTE/LED/KEY SW
P12
SS11
*VD,HD
P_ON/OFF
*Sub Filed Processor
X'tal
C22
SIGNAL
CONTROL
HDMI IN 1
DATA DRIVER(RIGHT)
AUDIO
F_STB+15V
DATA0
B[9:0],HD,VD
SS12
DC/DC
1.8V
1.8V
SOS8
IIC2
SW
PC IN
+15V
(UP)
64k
S.R.
S.R.
P5
REMOTE RECEIVER
VSUS
32Mbit
Flash-ROM
Flash-ROM
PULSE
STB5V
S.R.
SUSTAIN
AUDIO OUT
(4MByte)
AI SENSOR
C42
S.R.
S.R.
FLASH CONTROL
VOLTAGE
DC/DC
1.2V
1.2V
SW
128Mbit
DDR
DDR
P1.2V
D32
C12
S.R.
S.R.
PROM
C23
P25
C35
SS33
35
POWER
RECTIFIER
P11
DATA DRIVER(LEFT)
L/R
Vda
HDMI_SDIN
S.R.
PULSE
S
+15V
P5V
VOLTAGE
DIGITAL SIGNAL PROCESSOR
VDA_75V
D33
+5V
RESET
SOS8
S.R.
*Discharge Control
C4
STB12V
C40
DDR2x2
VOLTAGE
DRVRST
*RGB:10bit(or8bit)
P9
R,G,B
AVR
CARD
SPEAKER
R
AV TERMINAL
S.R.
RELAY
L/R
STB3.3V
ICEOUT
Vda
S.R.
CONTROL
P2
SC20
CONTROL
C30
Genx4
(DOWN)
CONTROL
SOUND_SOS
PCLK/NCLK
VIDEO
P3.3V
FILTER
V
REG
RESET
RESET
FRONT
L
D5
C32
PROCESS
S-VIDEO IN
STBY5V_M
12V
RECTIFIER
Discharge
Control(SS)
Control(SS)
VSUS
L
CLOCK
SOUND
SUSTAIN
VIDEO IN
FACTOR
C41
SC
*LVDS receiver
SOS
C33
VCXO
P5V
S.R.
SCAN
DG
51
51
VSUS
RECTIFIER
BOOT
ROM
ROM
Y,C,V
SOS6
SPEAKER
MAIN_L/R
PULSE
SS35
DTV_V
Data Driver
Control
Control
GENERATOR
PS_SOS
GS
LVDS format
D31
K1
VDA_75V
L/R
DRIVE
KEY SCAN
SW
P5V
Vda
AC CORD
Vda
DATA DRIVER(RIGHT)
GENERATOR
SD
AV3 IN
PA36
[27MHz]
VDA_75V
SCAN OUT
DCLK
FAN
K
VOLTAGE
FAN SOS
DG52
P2.5V
D3
NOR
FLASH
FLASH
VDA
G51
DC/DC CONVERTER
TUNER
DCK
S.R.
LINE
XRST
DIGITAL
S.R.
Y,Pb,Pr
S.R.
MAIN
SLOT
P10
FPGA
HDMI IN 2
C10
STANDBY
SCAN OUT
SS34
ANALOG
TUNER
SCART
AV1
COMP
SCART
VIDEO
AV2
L/R
L/R
V,R,G,B
V,Y,C
DC POWER
DG3
PA3
DC/DC
CONVERTER
CONVERTER
PA5
PA10
PA DC-DC CONVERTER
POWER SOS
FAN_SOS
FAN
SCAN
DRIVER
DRIVER
PA38
SCAN
DRIVER
DRIVER
G52
HEADPHONE
TH-42PY70FA/PA, PZ70BA/EA
Main Block Diagram
Main Block Diagram
TH-42PY70FA/PA, PZ70BA/EA
Main Block Diagram
Main Block Diagram
TH-42PY70FA / TH-42PY70PA / TH-42PZ70BA / TH-42PZ70EA
22
3.3. D-Board (1 of 2) Block Diagram
STB+3.3V
PANEL POWER PART SOS DET
P+5V FAIL VOLTAGE LED BLINKING
5 TIMES
P+15V OVER VOLTAGE LED BLINKING
2 TIMES
P+3.3V FAIL VOLTAGE LED BLINKING
3 TIMES
READ
Y
LED_R
STB_SD
A2
LED_R
PSLCT
MAIN_ON
RXD
TXD
P_ON/OFF
PSTB
TXD
RM
SOS4
LED_G
LED_G
PDB1
MAIN_ON
PDB0
PB
USY
PBUSY
P3V_SD
A1
ALARM
P3V_SCL1
STB_SDA2
PB
USY
P3V_SCL2
PSLCT
PSTB
P3V_SD
A2
PSTB
CLKM
PDB0
ALARM
SOS4
RXD
STB_SCL2
STB_SCL2
P_ON/OFF
STB_SCL2
RM
PDB1
RXD
VDA
P3V_SDA1
P3V_SCL1
PDB0
TXD
READY
STB_SDA2
DRVMUTE
PDB1
VD
A
P3V_SCL2
STB_SDA2
P3V_SDA2
STB_SCL2
P_CTL
WR_CTL
WR_CTL
XRST2
P3V_SDA1
P3V_SDA2
P3V_SCL2
P3V_SCL1
XRST
STBSDA2
STBSCL2
STB_SDA1
STB_SCL1
STB_SCL1
STB_SDA1
NRST2
NRST2
DR
VMUTE
PSLCT
SOS6_SC1
SOS7_SC2
SOS8_SS
DR
VRST
PRCK
Q9051
Q9054
P+1.2V
R9141
R9203
P+5V
Q9046
P+3.3V
Q9805
Q9806
Q9052
Q9044
Q9053
STB+5V
R9205
STB+5V
R9215
X9000
D9020
P+2.5V
Q9050
PA9800
P+15V
D9819
D9818
D9110
D9804
D9802
D9811
E+L
VDS0
10
RX
RA_E+
S CLOCK2
VD
OSD_HD
LVDS
12
OSC
PROCESSOR
11
53
50
20
84MHz
STBY+5V
14
4
OSD_B
20
10bit
92
15
36
REMOTE
15
P
ANEL SOS DET
OSD_R
10bit
ON/OFF
49
IIC_CONT
1
OSD_GI
23
7
D6
90
10
STB+3.3V/RESET
PDB0
OSD_CLKI
P+15V
STB+3.3V
21
16
P+3.3V/P+1.2V
2
ASDIO
PROCESSOR
EEPROM(FPGA)
13
HD
32
M_VDO
6
3
S D
A
T
A
1
1
DISCHARGE
CONTROL
CONTROL
24
9
TXD
27MHz
P+15V DET SOS2
37
STB+3.3V
RC_E-
G
STB+3.3V
M_HD0
18
PO
WER SOS DET
SOS4_PS
(LVDS_DET)
RXD
RC O-
P+15V
RCLK E-
ON/OFF
16
18
ECO_ON
17
LED R
DCLK
P25
PSLCT
OSD_CLKO
IIC_INT
IIC_CONT
PSTB
6
ON/OFF
OSD_G
2
86
PSLCT
P+3.3V
TXD
P+1.2V/P+2.5V/P+3.3V
21
6
RB O+
DISPEN
Vda SOS DET
33
IIC_CONT
20MHz
OSD_BI
18
PBUSY
DATA CONTROL(U)
CONT
21
B
IIC_DATA2
+3.3V
D
PDB1
S DATA1_IIC1_SDA
SUS CONTROL
RESET
84
RD O+
8
54
PSTB
34
IIC
P+15V SOS DET
2
10
LVDS_DET
6
VD
5
DG35
+3.3V
D5
RA O+
LED G
OSD_RI
IIC/INT
DATA CONTROL(D)
18
16
PDB0
PARALLE
11
16
PO
WER ST
A
TUS READ
Y
18
RXD
27
ALARM
9
RCLK O+
RA_E-
IIC_DATA1
70
RE O-
PDB1
SCAN CONTROL
IIC_CLK2
17
RB_E+
RC O+
DG5
TUNER_SUB_ON
PB
USY
PLASMA AI PROCESSOR
FOR
19
RD O-
FORMAT CONVERTER,
8
FACTORY USE
67
INV.
87
85
(1MB)
PSTB
72
HD
14
RC_E+
S CLOCK2_IIC2_SCL
TXD
30
P+5V SOS DET
21
P
ANEL MAIN ON/OFF
D3
RA O-
B
26
6
RESET
7
RE O+
10bit
69
NCS
S DATA2_IIC2_SDA
RD_E-
RD_E+
RE_E+
LED RED
12
4
DATA0
66
S CLOCK1_IIC1_SCL
P+3.3V DET SOS3
RXD
1
11
SUST
AIN
ENERGY RECO
VER
Y
SOS8_SS
23
10bit
43
RB_E-
3
25
S D
A
T
A
2
LED GREEN
P+1.2V
P+2.5V/P+3.3V ON/OFF
2
2
29
25
13
5
P+15V
RE_E-
31
STBY+5V
26
7
22
REMO
TE
1
4
F_STBY_ON
Q9010
TTL
ECO ON
14
P+5V
P15V
15
PB
USY
1
READY
PANEL_MAIN_ON
STBY5V
5
RCLK O-
93
VDATA_DET
71
MICOM
ALL_OFF
29
R
ALL_OFF
PSLCT
SOS4_PS
G
IIC_INT
91
7
RB O-
PANEL_STBY_ON
RCLK E+
19
17
PDB1
IIC_CLK1
P+5V DET SOS5
1
20
R
PDB0
17
10bit
D25
10bit
4
12
100
28
S CLOCK1
23
SYNC
DATA
7
9
19
SCAN ENEGR
Y RECO
VER
Y
SOS6_SC1
15
RGB
PICTURE
OUTPUT
(L)
(R)
PICTURE
OUTPUT
FLASH
CONTROL
(64k)
THERMAL SENSOR
1
EEPROM
6
P+3.3V
STB+3.3V
6
5
7
WP
XOUT
XIN
NRST
2
ALARM
SC FLO
A
T
ING P
A
R
T
SOS7_SC2
PANEL_STBY_ON
P_CTL
VCC
4
8
35
EEP_WR_CTL
LSI_RST
1
NRST
31
D5_DET0
3
DRIVER_RESET
XCE_L
P+3.3V
P+2.5V
P+1.2V
P+5V
+1.2V
IC9805
Q9807,Q9808
Q9809
+2.5V
IC9806
P+2.5V
SCL
SDA
SDA
SCL
VCC
30
P+5V
XRST2
4
8
11
6
3
13
1
4
10
9
12
14
2
5
IC9013
IIC SW
DCDC_ON
IC9007
VCC
7
VCC
3
8
VCC
STB+3.3V
27
DCLK
DATA0
ASDIO
28
26
29
NCS
DCLK
DATA0
ASDIO
NCS
P+1.2V
TDO
TRST
D9
3
TDI
TMS
P+3.3V
2
7
1
6
5
TCK
5
NRST2
D5_DET0
42
LVDS_DET
OSD_YSI
16
OSD_YS
20
OSD_VD
HD
VD
SCL
SD
A
NRST2
DR
V_MUTE
NRST
DRIVER RESET
(INTERNAL
FREE R
UN)
E-L
VDS0
E+L
VDS1
E-L
VDS1
E-L
VDS2
E+L
VDS3
E-L
VDS3
E+L
VDS2
E+L
VDSCLK
E+L
VDS4
E-L
VDS4
O+L
VDSCLK
E-L
VDSCLK
L
VDS_DET
O+L
VDS0
O-L
VDSCLK
O-L
VDS0
O+L
VDS1
O-L
VDS1
O+L
VDS2
O-L
VDS2
O+L
VDS3
O-L
VDS3
O+L
VDS4
O-L
VDS4
RE_E+
RE_E-
RD_E+
RD_E-
RC_E+
RC_E-
RB_E+
RB_E-
RA_E-
RA_E+
RCLK_E+
RCLK_E-
L
VDS_DET
RCLK_O+
RCLK_O-
RE_O+
RE_O-
RD_O+
RD_O-
RC_O+
RC_O-
RB_O+
RB_O-
RA_O+
RA_O-
SCAN CONTROL(42)
P+15V
JTAG
HD,VD
IC9011
IC9001
IC9002
IC9500
IIC_CONT
IIC_CONT
IIC
IC9003
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
FPGA
FACTORY USE
FOR
TH-42PY70FA/PA, PZ70BA/EA
D-Board (1 of 2) Block Diagram
D-Board (1 of 2) Block Diagram
TH-42PY70FA/PA, PZ70BA/EA
D-Board (1 of 2) Block Diagram
D-Board (1 of 2) Block Diagram
TH-42PY70FA / TH-42PY70PA / TH-42PZ70BA / TH-42PZ70EA
23
3.4. D-Board (2 of 2) Block Diagram
CPH1
CSOU
CPH2
CLK
CERS(CBK)
P3V_SCL2
P3V_SCL02
P3V_SD
A02
CEL
OCIA(CL)
CQR_(CPL)
SIUB/LA
T
SCSU
CSL
CML
P3V_SD
A2
OCK
PCK
CLKM
PRCK
SID
A
DRVRST
OC2(CEL2)
SIU
A
DR
V_RST0
OC1B(CL2)
CMH
SIDB(SID2)
CSH
SOS8_SS
SOS6_SC1
SOS7_SC2
ODEU1
LEU1
PCU1
CLR
U1
CLKU7(-)
CLKU6(+)
CLKU5(-)
CLKU4(+)
CLKU2(+)
P+3.3V
P+1.2V
P+2.5V
D9304
D9305
D9303
DET
2
60
33
D13C
SIUB/LA
T
(D22A-D31C)
67
35
VCC
8
(U10A-U15C)
68
59
60
DATA 30Bit
DDR-DRAM R
36
39
31
SCAN CONTROL
LED5
Q9303
13
5
DET
128Mbit
DATA PROCESS
2
C40
CLKU0(+)
14
3
75MHz
7
SUB FIELD
P+5V
DATA CONTROL 8bit
75MHz
36.6MHz
CLKD7(-)
41
1
CLKU6(+)
1
60
C41
61
*CONTOUR CORRE.
*S/P CONV.
3.3V->5V
DATA 18Bit
DATA PROCESS
SUSTAIN CONTROL
+5V
Q9301
32
MPEG
41
CLKD6(+)
DATA 18Bit
40
68
CLKU0(+)
P+5V
CLKU1(-)
9
11
42
37
PCD5
CLKU3(-)
PCK
USL
2
DDR-IO
CLKU7(-)
24
PCK
DET
CLKD3(-)
58
UMH
11
OCK
RESET
58
CLRD5
CLKD2(+)
6
+5V
UML
CLKD5(-)
CLRD6
128Mbit
DDR-DRAM L
28
ODED6
64
D36
64
CLKD4(+)
67
55
SC20
PCK
(D0A-D9C)
SIU
A
3.3V->5V
USH
VDD33
CEL
IIC
LED6
ODED5
4
35
CLK
19
CPH2
SCAN CONTROL
DATA 16bit
DATA 16bit
11
45
DATA 30Bit
+5V
34
CLKU5(-)
CONTROL
PROCESSOR
3.3V->5V
D10A
MPEG
8
CML
SOS8_SS
CLKD7(-)
NOISE REDUCTION
PCD6
2
29
PLASMA AI PROCESSOR
+5V
*DATA DRIVER
D
VDD25
P+2.5V
52
5
FORMAT CONVERTER,
P+5V
CONT
NUEL
LEVEL SHIFT
38
15
D22A
PROCESSOR
CLKD5(-)
66
(D16A-D21C)
LEVEL SHIFT
CLOCK
11
64
DET
PCD6
LED5
CLK OUT
*CONTOUR CORRE.
DATA 30Bit
63
56
LEVEL SHIFT
15
30
17
DATA 30Bit
DATA 18Bit
*S/P CONV.
OC2(CEL2)
28
*SF TABLE CONV.
FLASH
CLRD6
VCC
HD,VD
10
SUB FIELD
5
10
43
OCK
XRST2
*DATA DRIVER
66
G 10bit
OC1A(CL)
34
3
26
CLRD5
+5V DET
CLKU2(+)
38
VCC
14
D20
DATA
(U16A-U21C)
P+5V
I/F
54
CLKD4(+)
IIC
FLASH
P+5V
DATA
VCC
56
CLKD6(+)
13
67
37
CLOCK
17
D34
+5V DET
59
SID
A
BUS SWITCH
61
CERS(CBK)
36
(U0A-U9C)
DATA 4bit
58
1
OCK
ADR
8
9
16
7
P+5V
LED6
27
CLKD3(-)
ODED5
35
CSL
OCK
CSOU
VCC
DATA
DET
PCK
XRST
39
DATA 18Bit
(U22A-U31C)
59
C30
18
(D10A-D15C)
DDR-IO
UEH
DATA 6bit
36.6MHz
+5V
I/F
CLK OUT
*SF TABLE CONV.
D25C
5
Q9305
CLKU3(-)
CQR(CPL)
9
CONT
12
CONT
Q9302
34
ODED6
62
RESET
CPH1
10
VDDQ/VDD
RESET
P+5V
D35
VDD12
PCD5
33
31
10
SCSU
+5V DET
13
ADR
CLKU4(+)
84MHz
75MHz
VDD
36.6MHz
20MHz
X9200
CPG
CLKD1(-)
CLKD0(+)
CLKD3(-)
CLKD2(+)
CLKD6(+)
CLKD4(+)
CLKD5(-)
CLKD7(-)
ADDRESS
R 10bit
B 10bit
B 10bit
R 10bit
G 10bit
HD,VD
VDD12
VDD33
VDD25
BUS SWITCH
VCC
Q9300
DET
Q9304
+5V
Q9306
INV.
P+3.3V
P+1.2V
P+2.5V
21bit
G
B
10bit
10bit
10bit
R
9bit
P+3.3V
P+2.5V
P+1.2V
16bit
DATA
21bit
ADDRESS
16bit
DATA
16bit
DATA
NOISE REDUCTION
X1
X2
JTAG
DATA CONTROL
8bit
8bit
24
CMH
CSH
25
DR
V_RST0
SIDB(SID2)
OC1B(CL2)
26
22
27
NUEL
USL
USH
UMH
UEH
UML
32
CLKD0(+)
30
CLKD1(-)
CLKD3(-)
CLKD2(+)
CLKD3(-)
CLKD0(+)
CLKD1(-)
P+15V
6
21
30
31
SOS7_SC2
SOS6_SC1
P+15V
P+15V
D31C
D22A
D15C
D15A
D21C
D16A
D10A
D15C
JTAG
64
2
3
30
36
CLKU5(-)
35
5
38
31
13
P+5V
P+5V
U21C
67
68
U17A
1
66
56
CLKU2(+)
P+5V
34
39
+5V DET
33
CLKU4(+)
D32
U16A
28
26
43
U16C
41
67
U15C
24
2
U10A
45
C11
U16A
U21C
U10A
U15C
41
17
28
63
U22A
U27C
52
31
38
6
U28A
U31C
U22A
U31C
32
30
39
37
CLKU7(-)
CLKU6(+)
59
11
ODEU1
9
58
60
PCU1
LEU1
CLR
U1
10
8
61
68
1
3
+5V DET
P+5V
67
64
2
5
66
P+5V
P+5V
D9300
D9301
58
CLRU3
11
CLRU2
PCU3
10
PCU2
59
LEU3
8
ODEU3
9
LEU2
61
ODEU2
60
D31
C10
68
1
P+5V
2
3
P+5V
67
66
P+5V
D33
C20
64
+5V DET
D9302
5
36
33
35
37
39
34
32
30
CLKU1(-)
CLKU2(+)
CLKU3(-)
CLKU0(+)
CLKU2(+)
CLKU1(-)
U0A-U9C
52
31
38
U6A-U9C
17
63
28
6
41
U0A-U5C
67
66
P+5V
P+5V
68
P+5V
2
1
3
21
48
D0A-D1C
27
42
38
40
D3A-D3C
31
29
43
D2A-D2C
26
41
28
D4A-D9C
2
45
24
67
D0A-D9C
IC9304
IC9402
IC9504
IC9807
IC9802
IC9803
IC9803
IC9401
IC9400
IC9300
IC9301
IC9603
IC9200
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
PD1M+(MN84524) Right
PD1M+(MN84524) Left
16Mbit FlashROM
(PDROM)
D26A
D31C
D14C
D14A
D21C
D16A
TH-42PY70FA/PA, PZ70BA/EA
D-Board (2 of 2) Block Diagram
D-Board (2 of 2) Block Diagram
TH-42PY70FA/PA, PZ70BA/EA
D-Board (2 of 2) Block Diagram
D-Board (2 of 2) Block Diagram
TH-42PY70FA / TH-42PY70PA / TH-42PZ70BA / TH-42PZ70EA
24
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