DOWNLOAD Panasonic KX-TE82494X Service Manual ↓ Size: 1.14 MB | Pages: 18 in PDF or view online for FREE

Model
KX-TE82494X
Pages
18
Size
1.14 MB
Type
PDF
Document
Service Manual
Brand
Device
PBX / 3-PORT CALLER ID CARD
File
kx-te82494x.pdf
Date
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Panasonic KX-TE82494X Service Manual ▷ View online

13
KX-TE82494X
9 Appendix Information of Schematic Diagram
Note:
1. DC voltage measurements are taken with an oscilloscope or a tester with a ground.
2. The schematic diagrams and circuit board may be modified at any time with the development of new technology.
14
KX-TE82494X
10 Exploded View and Replacement Parts List
10.1. IC8
Pin No.
Terminal Name
I/O
Description
1
AVSS
-
GND (For analog interface) 
2
AVDD
-
Power Supply (3.3V: For analog interface)
3
AINP3
in
Amplifier input
4
AINM3
in
Amplifier input
5
GS3
out
Amplifier output
6
AIN3
in
ADC input
7
AINP2
in
Amplifier input
8
AINM2
in
Amplifier input
9
GS2
out
Amplifier output
10
AIN2
in
ADC input
11
AVSS
-
GND (For analog interface)
12
AVDD
-
Power Supply (3.3V: For analog interface)
13
AINP1
in
Amplifier input
14
AINM1
in
Amplifier input
15
GS1
out
Amplifier output
16
AIN1
in
ADC input
17
AINP0
in
Amplifier input
18
AINM0
in
Amplifier input
19
GS0
out
Amplifier output
20
AIN0
in
ADC input
21
VREF
out
Voltage Reference
22
AVSS
-
GND (For analog interface) 
23
AVDD
-
Power Supply (3.3V: For analog interface)
24
MODE3
in
Mode select bit (5V tolerant) 
25
MODE2
in
Mode select bit (5V tolerant) 
26
MODE1
in
Mode select bit (5V tolerant)
27
MODE0
in
Mode select bit (5V tolerant)
15
KX-TE82494X
28
VSS
-
GND (For internal ASIC)
29
VDD
-
Power Supply (2.5V: For internal Power of ASIC)
30
NIRQ
out
Interrupt output
31
NWAIT
out
Wait signal (Open Drain)
32
NWR
in
Write enable signal (Low Active) (5V tolerant)
33
NRD
in
Read enable signal (Low Active) (5V tolerant)
34
DATA7
I/o
Data bus (5V tolerant)
35
DATA6
I/o
Data bus (5V tolerant)
36
DATA5
I/o
Data bus (5V tolerant)
37
DATA4
I/o
Data bus (5V tolerant) 
38
DATA3
I/o
Data bus (5V tolerant) 
39
DATA2
I/o
Data bus (5V tolerant) 
40
VSSQ
-
GND (For ASIC I/O) 
41
VDDQ
-
Power Supply (3.3V: For ASIC I/O)
42
DATA1
I/o
Data bus (5V tolerant) 
43
DATA0
I/o
Data bus (5V tolerant) 
44
NCS1
in
Chip select signal (Low Active) (internal pull up) 
45
NCS0
in
Chip select signal (Low Active) (internal pull up) 
46
DEC_NOCS1
out
DECODE result (Low Active)
47
DEC_NOCS0
out
DECODE result (Low Active)
48
DEC_NCSI
in
Chip select signal (Low Active) of Address decoder (equivalent to 139) 
 (internal pull up) 
49
DEC_AD/ADD5
in
Address (Low Active) of Address decoder (equivalent to 139) 
 (internal pull up) 
It becomes the input terminal of ADD 5 at the extension mode.
50
ADD4
in
Address bus (5V tolerant) 
51
ADD3
in
Address bus (5V tolerant) 
52
ADD2
in
Address bus (5V tolerant) 
53
VSS
-
GND (For internal ASIC) 
54
VDD
-
Power Supply (2.5V: For internal Power of ASIC)
55
ADD1
in
Address bus (5V tolerant) 
56
ADD0
in
Address bus (5V tolerant) 
57
CLK_EN
in
System clock select terminal for ASIC shipment inspection
(Normal "H" input)  (5V tolerant) 
58
NRST
in
System reset (Low Active)  (Schmidt trigger input)  (5V tolerant) 
59
VDDQ
-
Power Supply for ASIC I/O (3.3V) 
60
VSSQ
-
GND for ASIC I/O
61
PLL_VCNT
in
Bias voltage for internal PLL
62
PLLVSS
-
GND for internal PLL
63
PLLVDD
-
Power Supply for internal PLL (2.5V) 
64
DT_STD3
out
Outside line mode: DTMF detection status (High Active) *not used
65
DT_STD2
out
Outside line mode: DTMF detection status (High Active) *not used
66
DT_STD1
out
Outside line mode: DTMF detection status (High Active) *not used
67
DT_STD0
out
Outside line mode: DTMF detection status (High Active) *not used
68
VDD
-
Power Supply (2.5V: For internal Power of ASIC)
69
VSS
-
GND (For internal ASIC) 
70
OSI
in
Crystal departure pendulum input terminal (4.096MHz)
71
OSO
out
Crystal departure pendulum output terminal (4.096MHz)
72
VSSQ
-
GND for ASIC I/O
73
TST_CLK
in
Clock input for factory inspection (normal “H” input) (5V tolerant)
74
SCAN_EN
in
Scan mode enable (normal “L” input) (5V tolerant) 
75
DT_TOE3/HWFH
in
Outside line mode : DTMF output enable
Extension mode : HW frame head (8kHz)  <TDA30 mode> (5V tolerant)
76
DT_TOE2/HWCP
in
Outside line mode : DTMF output enable
Extension mode : HW channel pulse <TDA100/200/600 mode> (5V toler-
ant) 
77
DT_TOE1/HWCLK
in
Outside line mode : DTMF output enable
Extension mode : HW clock (4.096MHz or 2.048MHz)  (5V tolerant)
78
DT_TOE0/UHWD
I/o
Outside line mode : DTMF output enable
Extension mode : Going up HW data (5V tolerant)
79
VDDQ
-
Power Supply for ASIC I/O (3.3V)
80
VSSQ
-
GND for ASIC I/O
81
PDATA/PIO7
I/o
The serial data for Pay Tone detection IC setting (5V tolerant)
82
PCLK/PIO6
I/o
Clock for Pay Tone setting (5V tolerant)
83
NPCS1/PIO5
I/o
Chip select signal for Pay Tone seting (5V tolerant)
84
NPCS0/PIO4
I/o
Chip select signal for Pay Tone seting (5V tolerant)
85
PDET3/PIO3
I/o
Detection signal of Pay Tone (5V tolerant)
86
PDET2/PIO2
I/o
Detection signal of Pay Tone (5V tolerant)
Pin No.
Terminal Name
I/O
Description
16
KX-TE82494X
10.2. Accessories and Packing Materials
87
PDET1/PIO1
I/o
Detection signal of Pay Tone (5V tolerant)
88
PDET0/PIO0
I/o
Detection signal of Pay Tone (5V tolerant)
89
VDD
-
Power Supply (2.5V: For internal Power of ASIC)
90
VSS
-
GND (For internal ASIC) 
91
PIN7
in
General-purpose input port (5V tolerant)
92
PIN6
in
General-purpose input port (5V tolerant)
93
PIN5
in
General-purpose input port (5V tolerant)
94
PIN4
in
General-purpose input port (5V tolerant)
95
PIN3
in
General-purpose input port (5V tolerant)
96
PIN2
in
General-purpose input port (5V tolerant)
97
PIN1
in
General-purpose input port (5V tolerant)
98
PIN0
in
General-purpose input port (5V tolerant)
99
VDDQ
-
Power Supply for ASIC I/O (3.3V)
100
VSSQ
-
GND for ASIC I/O
Pin No.
Terminal Name
I/O
Description
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