Panasonic KX-TDE600RU Service Manual ▷ View online
125
KX-TDE600RU
14 Appendix Information of Schematic Diagram
Note:
1. DC voltage measurements are taken with an oscilloscope or a tester with a ground.
1. The schematic diagrams and circuit board may be modified at any time with the development of new technology.
1. The schematic diagrams and circuit board may be modified at any time with the development of new technology.
126
KX-TDE600RU
15 Exploded View and Replacement Parts List
15.1. IC Data
15.1.1. IC101
Pin No.
Pin Name
I/O
Function
A1
VSSQ-DDR
-
DDR I/O GND
A2
VCCQ-DDR
-
DDR I/O VCC
A3
DDR-VREF
I
DDR VREF
A4
MCLK
O
DDR clock
A5
MCLK#
O
DDR clock
A6
MWE#
O
DDR write enable
A7
MRAS#
O
DDR RAS
A8
BA0
O
DDR bank address 0
A9
MA10
O
DDR address
A10
MA1
O
DDR address
A11
MA3
O
DDR address
A12
PRESET#
I
Power on reset
A13
DRAK1#/MODE7
O/I
DMA channel 1 transfer request acknowledge/mode control 7
A14
DREQ0#
I
DMA channel 0 request
A15
DREQ3#/INTC#/
AUDATA1
AUDATA1
I/I/O
DMA channel 3 request/PCI interrupt C/H-UDI emulator
A16
DACK2#/MRE-
SETOUT#/AUDATA2
SETOUT#/AUDATA2
O/O/O DMA channel 2 bus acknowledgment/manual reset output/H-UDI emulator
A17
TDI
I
H-UDI data
A18
AUDSYNC/FCE#
O/O
H-UDI emulator/NAND flash CE
A19
AUDATA1/FD1
O/IO
H-UDI emulator/NAND flash data
A20
SIOF_SYNC/
HAC_SYNC/SSI_WS
HAC_SYNC/SSI_WS
IO/O/IO SIOF flame synchronous/HAC flame synchronous/SSI word select
127
KX-TDE600RU
A21
SCIF1_TXD/MCCLK/
MODE5
MODE5
O/O/I
SCIF 1 transmit data/card clock output/mode control 5
A22
XTAL2
O
RTC clock
A23
EXTAL2
I
RTC crystal resonator
A24
VDD-RTC
-
RTC VDD
A25
VSS-RTC
-
RTC GND
B1
VSSQ-DDR
-
DDR I/O GND
B2
VCCQ-DDR
-
DDR I/O VCC
B3
BKPRST#
I
Back-up reset
B4
CKE
O
DDR clock enable
B5
MA13
O
DDR address
B6
MCAS#
O
DDR CAS
B7
MCS#
O
DDR chip select
B8
BA1
O
DDR bank address 1
B9
MA0
O
DDR address
B10
MA2
O
DDR address
B11
MA4
O
DDR address
B12
VSS
-
Internal GND
B13
DRAK2#/CE2A#/
AUDCK
AUDCK
O/O/O DMA channel 2 transfer request acknowledge/PCMCIA CE2/H-UDI emulator
B14
DREQ1#
I
DMA channel 1 request
B15
DACK0#/MODE0
O/I
DMA channel 0 bus acknowledgement/mode control 0
B16
DACK3#/IRQOUT#/
AUDATA3
AUDATA3
O/O/O DMA channel 3 bus acknowledgement/interrupt request output/H-UDI emulator
B17
TDO
O
H-UDI data
B18
AUDCK/FALE
O/O
H-UDI emulator/NAND flash ALE
B19
AUDATA0/FD0
O/IO
H-UDI emulator/NAND flash data
B20
SIOF_RXD/
HAC_SDIN/SSI_SCK
HAC_SDIN/SSI_SCK
I/I/IO
SIOF receive data/HAC serial data incoming to Rx frame/SSI serial bit clock
B21
SCIF1_SCK/MCCMD
IO/IO
SCIF1 serial clock/MMCIF command response
B22
SCIF0_RXD/
HSPI_RX/FRB
HSPI_RX/FRB
I/I/I
SCIF receive data/HSPI receive data input/NAND flash ready or busy
B23
TCLK/IOIS16#
IO/I
TMU clock/PCMCIA IOIS16
B24
XRTCSTBI#
I
RTC standby
B25
VSSQ
-
I/O GND
C1
MDA0
IO
DDR data
C2
VCCQ-DDR
-
DDR I/O VCC
C3
VSSQ-DDR
-
DDR I/O GND
C4
VCCQ-DDR
-
DDR I/O VCC
C5
MA12
O
DDR address
C6
MA11
O
DDR address
C7
MA9
O
DDR address
C8
MA8
O
DDR address
C9
MA7
O
DDR address
C10
MA6
O
DDR address
C11
MA5
O
DDR address
C12
DRAK0#/MODE2
O/I
DMA channel 0 transfer request acknowledge/mode control 2
C13
DRAK3#/CE2B#/
AUDSYNC
AUDSYNC
O/O/O DMA channel 3 request acknowledgment/PCMCIA CE2/H-UDI emulator
C14
DREQ2#/INTB#/
AUDATA0
AUDATA0
I/I/O
DMA channel 2 request/PCI interrupt B/H-UDI emulator
C15
DACK1#/MODE1
O/I
DMA channel 1 bus acknowledgement/mode control 1
C16
TCK
I
H-UDI clock
C17
ASEBRK#/BRKACK
I
H-UDI emulator
C18
AUDATA3/FD3
O/IO
H-UDI emulator/NAND flash data
C19
SIOF_SCK/
HAC_BITCLK/
SSI_CLK
HAC_BITCLK/
SSI_CLK
IO/I/IO SIOF serial clock/HAC/SSI serial bit clock
C20
SIOF_TXD/
HAC_SDOUT/
SSI_SDATA
HAC_SDOUT/
SSI_SDATA
O/O/IO SIOF transmit data/HAC serial data/SSI serial data
C21
SCIF0_RTS#/
HSPI_CS#/FSE#
HSPI_CS#/FSE#
IO/IO/O SCIF modem control/HSPI chip selection/NAND flash spare area enable
C22
SCIF0_TXD/HSPI_TX/
FWE#/MODE8
FWE#/MODE8
O/O/O/I SCIF0 transmit data/HSPI transmit data/NAND flash write enable/mode control
8
C23
SCIF0_SCK/
HSPI_CLK/FRE#
HSPI_CLK/FRE#
IO/IO/O SCIF0 serial clock/HSPI serial clock/NAND flash read enable
C24
VDDQ
-
I/O VDD
Pin No.
Pin Name
I/O
Function
128
KX-TDE600RU
C25
IRQ/IRL7#/FD7
I/IO
IRL IRQ interrupt request 7/NAND flash data
D1
MDA1
IO
DDR data
D2
MDA16
IO
DDR data
D3
VSSQ-DDR
-
DDR I/O GND
D4
VCCQ-DDR
-
DDR I/O VCC
D5
VSSQ-DDR
-
DDR I/O GND
D6
VSSQ-DDR
-
DDR I/O GND
D7
VCCQ-DDR
-
DDR I/O VCC
D8
VCCQ-DDR
-
DDR I/O VCC
D9
VSSQ-DDR
-
DDR I/O GND
D10
VSSQ-DDR
-
DDR I/O GND
D11
VCCQ-DDR
-
DDR I/O VCC
D12
VSSQ
-
I/O GND
D13
VDDQ
-
I/O VDD
D14
VDDQ
-
I/O VDD
D15
VSSQ
-
I/O GND
D16
TMS
I
H-UDI emulator
D17
TRST#
I
H-UDI emulator
D18
AUDATA2/FD2
O/IO
H-UDI emulator/NAND flash data
D19
SIOF_MCLK/
HAC_RES#
HAC_RES#
I/O
SIOF master clock/HAC reset
D20
SCIF1_RXD/MCDAT
I/IO
SCIF1 receive data/MMCIF data
D21
SCIF0_CTS/INTD#/
FCLE
FCLE
IO/I/O
SCIF modem control/PCI interrupt D
D22
VDD
-
Internal VDD
D23
VDD
-
Internal VDD
D24
IRQ/IRL6#/FD6/
MODE6
MODE6
I/IO/I
IRL IRQ interrupt request 6/NAND flash data/mode control 6
D25
IRQ/IRL5#/FD5/
MODE4
MODE4
I/IO/I
IRL IRQ interrupt request 5/NAND flash data/mode control 4
E1
MDA2
IO
DDR data
E2
MDA17
IO
DDR data
E3
MDA18
IO
DDR data
E4
VCCQ-DDR
-
DDR I/O VCC
E5
VSSQ-DDR
-
DDR I/O GND
E6
VSSQ-DDR
-
DDR I/O GND
E7
VCCQ-DDR
-
DDR I/O VCC
E8
VDD
-
Internal VDD
E9
VSS
-
Internal GND
E10
VSSQ-DDR
-
DDR I/O GND
E11
VCCQ-DDR
-
DDR I/O VCC
E12
VSSQ
-
I/O GND
E13
VDDQ
-
I/O VDD
E14
VDD
-
Internal VDD
E15
VSS
-
Internal GND
E16
VSSQ
-
I/O GND
E17
VSSQ
-
I/O GND
E18
VDDQ
-
I/O VDD
E19
VDDQ
-
I/O VDD
E20
VDDQ
-
I/O VDD
E21
VSSQ
-
I/O GND
E22
VDD
-
Internal VDD
E23
IRQ/IRL4#/FD4/
MODE3
MODE3
I/IO/I
IRL IRQ interrupt request 4/NAND flash data/mode control 3
E24
IRQ/IRL3#
I
IRL IRQ interrupt request 3
E25
IRQ/IRL2#
I
IRL IRQ interrupt request 2
F1
MDA3
IO
DDR data
F2
MDA19
IO
DDR data
F3
MDA20
IO
DDR data
F4
VCCQ-DDR
-
DDR I/O VCC
F5
VSSQ-DDR
-
DDR I/O GND
F21
VDDQ-PCI
-
PCI I/O VDD
F22
VDDQ-PCI
-
PCI I/O VDD
F23
IRQ/IRL1#
I
IRL IRQ interrupt request 1
F24
IRQ/IRL0#
I
IRL IRQ interrupt request 0
F25
NMI
I
Nonmaskable interrupt
G1
MDA4
IO
DDR data
Pin No.
Pin Name
I/O
Function
