DOWNLOAD Panasonic KX-TDA6382X / KX-TDA6382SX Service Manual ↓ Size: 8.07 MB | Pages: 85 in PDF or view online for FREE

Model
KX-TDA6382X KX-TDA6382SX
Pages
85
Size
8.07 MB
Type
PDF
Document
Service Manual
Brand
Device
PBX / 16-PORT ANALOGUE TRUNK CARD WITH CID16
File
kx-tda6382x-kx-tda6382sx.pdf
Date

Panasonic KX-TDA6382X / KX-TDA6382SX Service Manual ▷ View online

9
KX-TDA6382X/KX-TDA6382SX
4.2.1.3.
ASIC...IC3
• EC bus Interface
16bit/8MHz two-way address data multiplex self-bus (communication bus with MPR)
• CT bus Interface
Supports eight of 8.192MHz highway (128 timeslot) (voice communication bus with MPR)
• Local TSW
Timeslot switching between CT bus (1024ch) and local highway (64ch)
(Timeslot switching between the voice communication bus in MPR and that in the circuit board)
• Local Gain Control
Gain control of the local highway up-down 64ch by 1dB/step randomly
• GPIO Interface
A parallel interface that can be set in random interactively
Refer to IC3 (ASIC) (P.64).
Host-EC
bridge
(slave)
CT_IF
Local
TSW
Host
Local-bus I/F
DPLL
JTAG
GAIN
Internal Highway
Internal bus
System bus
APT
controller
HDLC
8ch
FIFO/
DPRAM
DPT
controller
Local
Highway I/F
PT
DR/RV
GPIO
CODEC
Controller
RT_SND
CS-IF
Local
Bus
EC
CT
Highway
PT-I/F
GPIO-i/f
CS-I/F
10
KX-TDA6382X/KX-TDA6382SX
4.2.1.4.
8-Port Sub Board
8-Port Sub Board is mounterd  to Main Board.
DT_OE[15]
DT_OE[11]
DT_OE[13]
DT_OE[12]
DT_OE[14]
DT_OE[8]
DT_OE[9]
DT_OE[8-15]
D[0-7]
DT_OE[10]
DT_OE[13]
DT_OE[15]
LA[0-5]
DT_OE[9]
R[14]
R[15]
R[8]
R[10]
R[9]
R[11]
R[13]
R[12]
T[8]
DT_OE[8]
LA[1]
LA[2]
LA[5]
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
LA[4]
LA[0]
LA[3]
DT_OE[12]
T[9]
T[10]
T[11]
T[12]
T[13]
T[14]
T[15]
DT_OE[11]
DT_OE[14]
DT_OE[10]
OPT[1]
DG
DG
CLK
FH
DHW
UHW
C_CS[2]
C_CS[3]
DCLK
DIN
DOUT
DG
+5V
nRD
CLK
nWR
nCS_CID[1]
nRST
11
19
31
17
18
49
57
22
56
28
52
21
51
48
55
2
1
47
3
29
30
59
34
33
53
23
4
45
60
17
25
27
15
13
19
26
54
6
5
7
38
3
9
32
12
8
8
13
CN8
5
24
20
46
50
16
43
40
58
39
7
10
15
41
11
42
14
36
35
6
37
9
12
44
CN2
12
34
CN2
9
CN2
10
35
37
CN2
11
36
CN2
13
38
CN2
14
39
CN2
15
40
CN2
16
41
5
6
7
8
5
6
7
8
CN6
1
2
14
16
18
4
10
20
J1I
J1J
J1K
J1L
J1M
J1N
J1O
J1P
SFG
+3.3V
+2.5V
DG
TH1I
TH1J
TH1K
TH1L
TH1M
TH1N
TH1O
TH1P
+15V
DG
C
928
C
929
C
930
C
931
SFG
C9
1
C9
0
RA
6
R
A
5
11
KX-TDA6382X/KX-TDA6382SX
4.2.2.
Description of Functions and Circuits
4.2.2.1.
Dial Pulse Signal Transmission
Transmits 10pps/20pps dial pulse by a open/close action between Tip and Ring with Photo MOS relay.
The make width, break width and inter digital width for 10pps/20pps can be set respectively.
When making, 37pin (DIAL [0]) of IC6 becomes Low level, and RL3 turns ON. When breaking, 37pin (DIAL [0]) of IC6 becomes
High level, and RL3 turns OFF.
It provides the SHUNT control function for the stabilization of line power depending on the destination. Turning ON PC5 when
transmitting pulse reduces the impedance at making, and stabilizes the line power.
4.2.2.2.
Circuit For Line Acquisition
Making CODEC (e.g. pin-37 of IC6, DIAL [0]) Low level, the photo MOS relay (RL3) turns ON and the line is acquired.
It is used in common as Dial Pulse transmitting circuit.
DC Loop Path:
• Ring
L1D1D2J7D3RL3Q4(C-E)D4D3L1TH1Tip
• Tip
TH1L1D3D4Q4(C-E)RL3D3J7D2D1L1Ring
R[0]
T[0]
AG
+5V
DG
DG
DG
DG
DG
+5V
+5V
+5V
+5V
+5V
SFG
R
20A
PC5A
1
2
3
4
R
17A
D2A
R3
A
T1A
2
1
3
4
C1
A
C2
A
C4
A
C8A
D1A
D4
A
R21A
R
11A
R
14A
R15A
R16A
R1
8
A
R
19A
R1
A
R22A
R2
A
R4A
1.2K
R5
A
R6
A
J1A
RL
2
A
4
3
2
1
J4A
PC1A
1
23
4
PC2A
1
2
3
4
PC
4
A
1
2
3
4
L1A
1
2
3
4
C3
A
CN3 2
CN3 3
J7
A
C6
A
C7A
Q5A
E
C
B
ZN
R
2
A
CN2
1
26
D3A
1
2
3
4
TH1A
ZN
R
1
A
RL3A
4
3
2
1
D5
A
SA
1
A
12
3
Q4A
E
C
B
A
Ring
Tip
CODEC
IC6
R[0]
T[0]
AG
+5V
DG
DG
DG
DG
DG
+5V
+5V
+5V
+5V
+5V
SFG
R
20A
PC5A
1
2
3
4
R
17A
D2A
R3
A
T1A
2
1
3
4
C1
A
C2
A
C4
A
C8A
D1A
D4
A
R21A
R
11A
R
14A
R15A
R16A
R
18A
R
19A
R1
A
R22A
R2
A
R4A
R5
A
R6
A
J1A
RL
2
A
4
3
2
1
J4A
PC1A
1
23
4
PC2A
1
2
3
4
PC
4
A
1
2
3
4
L1A
1
2
3
4
C3
A
CN3 2
CN3 3
J7
A
C6
A
C7A
Q5A
E
C
B
ZN
R
2
A
CN2
1
26
D3A
1
2
3
4
TH1A
ZN
R
1
A
RL3A
4
3
2
1
D5
A
SA
1
A
12
3
Q4A
E
C
B
A
Ring
Tip
CODEC
IC6
12
KX-TDA6382X/KX-TDA6382SX
4.2.2.3.
DTMF Signal Transmission
This transmits the DTMF signal on the highway timeslot. The different DTMF signals can be transmitted to the optional ports at
the same time.
They are transmitted to the line through CODEC.
4.2.2.4.
Bell Signal Detection
During on-hook, transmitting the bell signal to the AC loop in the CR series circuits (C3 and R5) detects the current by Photo
Coupler (PC1,2), and it determines the presence of a bell signal. Software performs the operation for recognition and determina-
tion of a pattern of bell signals.
Bell loop path
•  Ring
L1R2PC2(1-2)C3R5L1TH1Tip
In this path, PC1 4-pin converts from High to Low, and a bell signal is detected.
•   Tip
TH1L1R5C3PC2(1-2)R2L1Ring
In this path, PC2 4-pin converts from High to Low, and a bell signal is detected.
VIN[0]
DIAL[0]
VOUT[0]
CPCDET[0]
SHNT[0]
VH1
+15V
DG
+5V
AG
+5V
AG
R20A
PC5A
1
2
4
R32A
T1A
2
1
3
4
C10A
C11A
C12A
C16A
C8A
C9A
IC1A
1
2
3
4
8
R21A
R22A
R24A
R27A
R30A
R34A
R35A
DA1A
1
2
3
C7A
IC1A
5
6
7
R23A
DTMF signal
CODEC
R[0]
T[0]
AG
+5V
DG
DG
DG
DG
DG
+5V
+5V
+5V
+5V
+5V
SFG
R
20A
PC5A
1
2
3
4
R
17A
D2A
R3
A
T1A
2
1
3
4
C1
A
C2
A
C4
A
C8A
D1A
D4
A
R21A
R
11A
R
14A
R15A
R16A
R
18A
R
19A
R1
A
R22A
R2
A
22
R4A
1.2K
R5
A
R6
A
J1A
RL
2
A
4
3
2
1
J4A
PC1A
1
23
4
PC2A
1
2
3
4
PC
4
A
1
2
3
4
L1A
1
2
3
4
C3
A
CN3 2
CN3 3
J7
A
C6
A
C7A
Q5A
E
C
B
ZN
R
2
A
CN2
1
26
D3A
1
2
3
4
TH1A
ZN
R
1
A
RL3A
4
3
2
1
D5
A
SA
1
A
12
3
Q4A
E
C
B
A
Ring
Tip
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