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Model
KX-TDA6382X KX-TDA6382SX
Pages
85
Size
8.07 MB
Type
PDF
Document
Service Manual
Brand
Device
PBX / 16-PORT ANALOGUE TRUNK CARD WITH CID16
File
kx-tda6382x-kx-tda6382sx.pdf
Date

Panasonic KX-TDA6382X / KX-TDA6382SX Service Manual ▷ View online

6
KX-TDA6382X/KX-TDA6382SX
4 Technical Descriptions
4.1.
Block Diagram
4.1.1.
Block Diagram of Main Board
BACK
B
O
A
RD
L_NRST
W R
RD
MODE[5:0]
P1[7:0]
nRESET
PLLCLK
DIN
DOUT
DCLK
C_CS[0]
FH
HW CLK[0]
LDHW [0]
LUHW [0]
EC_CLK
EC_AD[15:0]
EC_PAR
EC_FRAME
EC_TRDY
EC_STOP
EC_BE[1:0]
EC_PERR
EC_INT
EC_IDSEL
EC_NRST
CT_NETREF
CT_FRAME_A
CT_C8_A
CT_D[7:0]
A[4:0]
D[7:0]
ASIC
(CIDA
nRD,nW R,nRST
JUMPER
RESET
IC
XTAL
16.384
MHz
JUMPER
C_CS[0]
DHW [0]
ASIC
(TACKER2)
UHW [0]
CLK
FH
DOUT
DXA
DXB
PCLK
MCLK
DIN
DCLK
DRA
DRB
CODEC
PEB
2466
FSC
RESET
EC_DET
CT_CB_A
DEC_NCSI
NRD
NRST
NW R
nCS1
DRIVER
DRIVER
P22
P23
+3.3V
nCPCDET[0]
SHUNT[0]
OP AMP
Rev&Bell
&Shunt
Detector
Port A
Transformer
DIAL &
DC Loop &
CPC
Detector
nBELDET[0]
nLOOP[0]
Serge
EMC
nREVDET[0]
OP AMP
Rev&Bell
&Shunt
Detector
Port B
Transformer
DIAL &
DC Loop &
CPC
Detector
nBELDET[
䠍]
nLOOP[
䠍]
Serge
EMC
nREVDET[
䠍]
OP AMP
Rev&Bell
&Shunt
Detector
Port C
Transformer
DIAL &
DC Loop &
CPC
Detector
nBELDET[
䠎]
nLOOP[
䠎]
Serge
EMC
nREVDET[
䠎]
OP AMP
Rev&Bell
&Shunt
Detector
Port D
Transformer
DIAL &
DC Loop &
CPC
Detector
nBELDET[
䠏]
nLOOP[
䠏]
Serge
EMC
nREVDET[
䠏]
nCPCDET[
䠍]
SHUNT[
䠍]
nCPCDET[
䠎]
SHUNT[
䠎]
nCPCDET[
䠏]
SHUNT[
䠏]
+5V
+3.3V
+15VPT
+15V
+40V
DC/DC
DC/DC
+2.5V
Series
Reg
DXA
DXB
PCLK
MCLK
DIN
DCLK
CS
DRA
DRB
CODEC
PEB
2466
FSC
RESET
nCPCDET[
䠐]
SHUNT[
䠐]
OP AMP
Rev&Bell
&Shunt
Detector
Port E
Transformer
DIAL &
DC Loop &
CPC
Detector
nBELDET[
䠐]
nLOOP[
䠐]
Serge
EMC
nREVDET[
䠐]
OP AMP
Rev&Bell
&Shunt
Detector
Port F
Transformer
DIAL &
DC Loop &
CPC
Detector
nBELDET[
䠑]
nLOOP[
䠑]
Serge
EMC
nREVDET[
䠑]
OP AMP
Rev&Bell
&Shunt
Detector
Port G
Transformer
DIAL &
DC Loop &
CPC
Detector
nBELDET[
䠒]
nLOOP[
䠒]
Serge
EMC
nREVDET[
䠒]
OP AMP
Rev&Bell
&Shunt
Detector
Port H
Transformer
DIAL &
DC Loop &
CPC
Detector
nBELDET[
䠓]
nLOOP[
䠓]
Serge
EMC
nREVDET[
䠓]
nCPCDET[
䠑]
SHUNT[
䠑]
nCPCDET[
䠒]
SHUNT[
䠒]
nCPCDET[
䠓]
SHUNT[
䠓]
nRES
DIN
FH
C_CS[1]
DHW [0]
UHW [0]
CLK
Connect to
ASIC(TACKER2)
C
onnector
to
S
u
b
boar
d
(P
or
t
I
P)
T/R[0]
T/R[1]
T/R[2]
T/R[3]
T/R[4]
T/R[5]
T/R[6]
T/R[7]
C_CS[2:3]
4M_CLK
+15V
+5V
+3.3V
+2.5V
T/R[8~15]
+15V
A[21:0]
D[15:0]
nRD
nW R
XTAL
12.288MHz
nCS[2:0]
BOARD
ID
3
nRESET
nIRQ1
nIRQ0
nBREQ
nBACK
NMI
nW DTOVF
FlashROM
RAM
nW R
nRD
nRD
nCS
nCS
A[18:0]
A[17:0]
D[15:0]
D[7:0]
nW R
nRESET
D[7:0]
A[5:0]
nRD,nW R,nRST
A[4:0]
D[7:0]
ASIC
(CIDA
DEC_AD
NRST
NW R
A[12:0]
D[7:0]
nBREQ
CPU
nBACK
nIRQ
nCSI
nHALT
LED Green
LED Red
nRST
CSI
LD
LA
HW _CLK[1]
C_CS[2-3]
nRES
DIN
DOUT
DCLK
nCS_CID[1]
CS[1]
nCS1
nRD,nW R,nRST
nCS_CID[0]
nRD,nW R,nRST
DEC_NOCS1
NCS0
nRD,nW R,nRST
nRD,nW R,nRST
nCS0
nRD,nW R
nCS2
DOUT
DOUT
DCLK
A[5]
T/R[3:0]
T/R[7:4]
KX-TDA6382
Main Board
Block Diagram
7
KX-TDA6382X/KX-TDA6382SX
4.1.2.
Block Diagram of Sub Board
nRES
A[4:0]
D[7:0]
ASIC
(CIDAك
nWR
nRD
nRES
C_CS[2]
DHW[0]
UHW[0]
CLK
FH
DOUT
DXA
DXB
PCLK
MCLK
DIN
DCLK
CS
DRA
DRB
CODEC
PEB
2466
FSC
RESET
NCS0
NWR
NRST
NRD
nCS[0]
nCPCDET[0]
SHUNT[0]
Rev&Bell
&Shunt
Detector
Port I
Transformer
DIAL &
DC Loop &
CPC
Detector
nBELDET[0]
nLOOP[0]
Serge
EMC
nREVDET][0]
OP AMP
Rev&Bell
&Shunt
Detector
Port J
Transformer
DIAL &
DC Loop &
CPC
Detector
nBELDET[ڭ]
nLOOP[ڭ]
Serge
EMC
nREVDET][ڭ]
OP AMP
Rev&Bell
&Shunt
Detector
Port K
Transformer
DIAL &
DC Loop &
CPC
Detector
nBELDET[ڮ]
nLOOP[ڮ]
Serge
EMC
nREVDET][ڮ]
OP AMP
Rev&Bell
&Shunt
Detector
Port L
Transformer
DIAL &
DC Loop &
CPC
Detector
nBELDET[㸱]
nLOOP[㸱]
Serge
EMC
nREVDET][㸱]
nCPCDET[ڭ]
SHUNT[ڭ]
nCPCDET[ڮ]
SHUNT[ڮ]
nCPCDET[㸱]
SHUNT[㸱]
+2.5V
+2.5V
DXA
DXB
PCLK
MCLK
DIN
DCLK
CS
DRA
DRB
CODEC
PEB
2466
FSC
RESET
nCPCDET[ڰ]
SHUNT[ڰ]
OP AMP
Rev&Bell
&Shunt
Detector
Port M
Transformer
DIAL &
DC Loop &
CPC
Detector
nBELDET[ڰ]
nLOOP[ڰ]
Serge
EMC
nREVDET][ڰ]
OP AMP
Rev&Bell
&Shunt
Detector
Port N
Transformer
DIAL &
DC Loop &
CPC
Detector
nBELDET[ڱ]
nLOOP[ڱ]
Serge
EMC
nREVDET][ڱ]
OP AMP
Rev&Bell
&Shunt
Detector
Port O
Transformer
DIAL &
DC Loop &
CPC
Detector
nBELDET[ڲ]
nLOOP[ڲ]
Serge
EMC
nREVDET][ڲ]
OP AMP
Rev&Bell
&Shunt
Detector
Port P
Transformer
DIAL &
DC Loop &
CPC
Detector
nBELDET[ڳ]
nLOOP[ڳ]
Serge
EMC
nREVDET][ڳ]
nCPCDET[ڱ]
SHUNT[ڱ]
nCPCDET[ڲ]
SHUNT[ڲ]
nCPCDET[ڳ]
SHUNT[ڳ]
A[4:0]
D[7:0]
ASIC
(CIDAك
NCS0
NWR
NRST
NRD
+2.5V
+2.5V
nRES
DIN
C_CS[0]
DHW[0]
UHW[0]
CLK
FH
nWR
nRD
nRES
T/R[8]
T/R[9]
T/R[10]
T/R[11]
T/R[12]
T/R[13]
T/R[14]
T/R[15]
+15V
+5V
+3.3V
+2.5V
Connector
fr
om
Main
boa
rd
(CO
L
ine)
Connect to
Control & Power line
connector
C_CS[3]
DOUT
4MCLK +15V
OP AMP
T/R [11:8]
DEC_AD
A[5]
OSI
OSI
Connector
fr
o
m
Main
Boa
rd
(Contr
o
l
&
power
L
in
e
)
T/R [15:12]
KX-TDA6382
Sub Board
Block Diagram
8
KX-TDA6382X/KX-TDA6382SX
4.2.
Circuit Operations
4.2.1.
Description of Control System Circuits 
4.2.1.1.
Reset
On startup, releasing the ASIC reset is executed by EC_nRST through MPR.
After releasing the ASIC, the local reset signal should be sent to CODEC by releasing the soft rest from MPR, and CODEC fac-
tor should be downloaded from MPR.
• LED operational state display LED (2 colors)
Red ON: Fault (includes RESET)
Green ON: INS (line free)
Green flash (60/sec): INS (line busy)
Red flash (60/sec): OUS
OFF: the power section failure
4.2.1.2.
Local Highway Interface
Packs 2.048, 4.096, 8.192 MHz highway (Max.64 timeslot). (voice communication bus in the circuit board)
The PCM data of arbitrary streams 0~15 (128 timeslot / 1 stream) on the CT bus can switch to the arbitrary local highway (64
timeslot) by the local TSW.
The timeslot configuration example of the local highway is shown below.
Timeslots between slot 8 and slot 15 are used by the Sub Board.
Slot
PCM Data
Slot
PCM Data
Slot
PCM Data
0
CO#1
16
Not used
32-63
Not used
1
CO#2
17
Not used
2
CO#3
18
Not used
3
CO#4
19
Not used
4
CO#5
20
Not used
5
CO#6
21
Not used
6
CO#7
22
Not used
7
CO#8
23
Not used
8
CO#9
24
Not used
9
CO#10
25
Not used
10
CO#11
26
Not used
11
CO#12
27
Not used
12
CO#13
28
Not used
13
CO#14
29
Not used
14
CO#15
30
Not used
15
CO#16
31
Not used
Software reset
EC_nRST
IC3
Reset IC
IC4
+5V
+3.3V
+3.3V
+3.3V
(Green)
LED
(Red)
P22
P23
nHALT
U1-1/2
Q3
System reset in ASIC
E
C
B
U
S
LPR reset
ASIC
RST
LED
CPU
IC401
nlRQ0
nRES
9
KX-TDA6382X/KX-TDA6382SX
4.2.1.3.
ASIC...IC3
• EC bus Interface
16bit/8MHz two-way address data multiplex self-bus (communication bus with MPR)
• CT bus Interface
Supports eight of 8.192MHz highway (128 timeslot) (voice communication bus with MPR)
• Local TSW
Timeslot switching between CT bus (1024ch) and local highway (64ch)
(Timeslot switching between the voice communication bus in MPR and that in the circuit board)
• Local Gain Control
Gain control of the local highway up-down 64ch by 1dB/step randomly
• GPIO Interface
A parallel interface that can be set in random interactively
Refer to IC3 (ASIC) (P.64).
Host-EC
bridge
(slave)
CT_IF
Local
TSW
Host
Local-bus I/F
DPLL
JTAG
GAIN
Internal Highway
Internal bus
System bus
APT
controller
HDLC
8ch
FIFO/
DPRAM
DPT
controller
Local
Highway I/F
PT
DR/RV
GPIO
CODEC
Controller
RT_SND
CS-IF
Local
Bus
EC
CT
Highway
PT-I/F
GPIO-i/f
CS-I/F
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