DOWNLOAD Panasonic KX-TDA6178X / KX-TDA6178XJ Service Manual ↓ Size: 2.85 MB | Pages: 67 in PDF or view online for FREE

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KX-TDA6178X/KX-TDA6178XJ BLOCK DIAGRAM

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IC100

6

• CPU (System clock: 12.288 MHz)......IC601

Data bus: 16bit, Address bus: 23bit

• Flash ROM (512Kbyte)......IC602

Flash memory consists of two areas: boot space and administration space.
Administration program can be rewritten through downloading.

• SRAM (1Mbit)......IC603

Used for the data buffer for CPU work area, and SLT communication.

• Reset

Resets of an ECSLC24 card are roughly classified into the two kinds: ASIC reset and LPR reset.
After the release of the ASIC reset, the LPR reset is released by the soft reset from the side of the main card and the LPR pro-
gram is booted.
For approx. 1 second after LPR reset until the Config reset signal (Done pin) in FPGA is cancelled, access to FPGA is
restricted.First check configuration in FPGA is complete, then start accessing.

Type of reset

Reset method

Specification

ASIC reset

ASIC reset is reset under the AND condition of reset signals (negative logic)
listed below.

Power-on reset

Reset by reset IC

Hard reset from the main bus

Reset by EC_RST signal

Soft reset from the main bus

Released after the specified time

LPR reset

Soft reset from the main bus

Low active
Reset pulse width: 1.6 microseconds or more

7

• LED Operation status indicating LED (Two colors)

OFF: Fault
Red ON: Fault (RESET included)
Green ON: Normal (Line not in use)
Green Flash (60/minute): Normal (Line in use)
Orange: OUS (Because OUS needs to be controlled by MPR, reset terminal and port control terminal are Red Blinking: OUS to
generate OUS)

• Instantaneous power interruption operation

When instantaneous power interruption is 300msec or less, reset operation is not carried out because the voltage is retained by
the capacitor in the power supply.
After HALT from MPR is detected at the DC power down port, CPU goes into the sleep mode by executing the instruction of
SLEEP.
At the sleep mode, the CPU/Clock enters the halt state while the contents of the register, the internal RAM, and the I/O port are
maintained.
When the instantaneous power interruption is released, HALT is negated, and CPU is recovered to the normal mode by the
detection of IRQ0=L

8

• EC bus interface

Independent bus for 16bit/8MHz two-way address data multiplex.

• CT bus interface

Supports eight 8.192MHz highways (128 time slots).

• Local TSW

Exchanges the time slots between CT bus (1024ch) and local highway (64ch).

• Local highway interface

Accommodates 2.048, 4.096, and 8.192MHz highways (Up to 64 time slots).

• Local gain control

Controls the gain of the local highway up-and-down 64ch in 1db step arbitrarily.