DOWNLOAD Panasonic KX-TDA6178X / KX-TDA6178XJ Service Manual ↓ Size: 2.85 MB | Pages: 67 in PDF or view online for FREE

4

This card is plugged into a free slot on the TDA600 systems and randomly connects up to 24 SLT devices.
Can only be installed in shelves in which a PSU-L is intalled.
This card sends Caller ID signal to extension ports.
The LPR is SH-1(SH7020), and the memory is composed of a 512K byte Flash ROM and a 128K byte SRAM.
It also supports a software upgrade by downloading the latest version.

Functional Block

Functional contents

Extension Interface

Number of Ports

24 ports

SLT Interface

-26V 26mA Feeding function
(Voltage in ports 1-8 are switched over to -45V, depending on the circuit dis-
tance.)
Dial-pulse signal detecting function
DTMF signal detecting function
Bell signal issuing function
Hook detecting function
Ringtrip detecting function
2W/4W converting function
Surge protective function
CODEC function

• Test function (Loop back, Tone generation)
• Programmable digital filtering function
• Serial interface function
• PIO function

DTMF Receiver

24 lines for each port

Caller ID (FSK)

24 lines for each port

On-board Ringer

20/25Hz 75Vrms
Phase control (Three-phase / Four-phase)

On-board DC/DC Power Supply

Input +15V
Output +3.3V
Input +40V
Output: -30V, -55V, +80V

Power Failure Forwarding Function

4 lines supported

Self-Diagnostic Function

Carried out with outside-line interface in a pair (only one port)
Speech path test, Dial pulse test, DTMF test

ASIC

EC bus interface function
H.100 bus interface function, Digital PLL function
Local bus interface function
Time switch function, Gain controlling function, FIFO/DPRAM function
Intelligent PIO function

Control Unit

CPU

SH-1/SH7020 (12.288MHz)

Flash ROM

512Kbyte

SRAM

128Kbyte

FPGA

• Interface between codec and CPU
• SRAM type (XC3S250E) manufactured by XILINX
• CID128 bytes /ch transmission buffer 

LED Display Circuit

Card status indicating LED: Two colors (Red/Green)

External Interface Connector

Extension interface

50pin Amphenol connector: 1

Power failure forwarding 4pin modular jack: 2

5

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6

• CPU (System clock: 12.288 MHz)......IC601

Data bus: 16bit, Address bus: 23bit

• Flash ROM (512Kbyte)......IC602

Flash memory consists of two areas: boot space and administration space.
Administration program can be rewritten through downloading.

• SRAM (1Mbit)......IC603

Used for the data buffer for CPU work area, and SLT communication.

• Reset

Resets of an ECSLC24 card are roughly classified into the two kinds: ASIC reset and LPR reset.
After the release of the ASIC reset, the LPR reset is released by the soft reset from the side of the main card and the LPR pro-
gram is booted.
For approx. 1 second after LPR reset until the Config reset signal (Done pin) in FPGA is cancelled, access to FPGA is
restricted.First check configuration in FPGA is complete, then start accessing.

Type of reset

Reset method

Specification

ASIC reset

ASIC reset is reset under the AND condition of reset signals (negative logic)
listed below.

Power-on reset

Reset by reset IC

Hard reset from the main bus

Reset by EC_RST signal

Soft reset from the main bus

Released after the specified time

LPR reset

Soft reset from the main bus

Low active
Reset pulse width: 1.6 microseconds or more

7

• LED Operation status indicating LED (Two colors)

OFF: Fault
Red ON: Fault (RESET included)
Green ON: Normal (Line not in use)
Green Flash (60/minute): Normal (Line in use)
Orange: OUS (Because OUS needs to be controlled by MPR, reset terminal and port control terminal are Red Blinking: OUS to
generate OUS)

• Instantaneous power interruption operation

When instantaneous power interruption is 300msec or less, reset operation is not carried out because the voltage is retained by
the capacitor in the power supply.
After HALT from MPR is detected at the DC power down port, CPU goes into the sleep mode by executing the instruction of
SLEEP.
At the sleep mode, the CPU/Clock enters the halt state while the contents of the register, the internal RAM, and the I/O port are
maintained.
When the instantaneous power interruption is released, HALT is negated, and CPU is recovered to the normal mode by the
detection of IRQ0=L