Panasonic KX-TDA100DUP Service Manual ▷ View online
101
KX-TDA100DUP
14 Appendix Information of Schematic Diagram
Note:
1. DC voltage measurements are taken with an oscilloscope or a tester with a ground.
2. The schematic diagrams and circuit board may be modified at any time with the development of new technology.
2. The schematic diagrams and circuit board may be modified at any time with the development of new technology.
102
KX-TDA100DUP
15 Exploded View and Replacement Parts List
15.1. IC Data
15.1.1. IC5
Pin No.
Pin Name
I/O
Description
1
MD1
I
Clock mode setting
2
MD2
I
Clock mode setting
3
Vcc-TRC*1
-
Power for RTC
4
XTAL2
O
Crystal oscillator terminal for built-in RTC
5
EXTAL2
I
Crystal oscillator terminal for built-in RTC (*6)
6
Vcc-TRC*1
-
Power for RTC
7
NMI
I
Nonmaskable interrupt request
8
IRQ0/IRL0/PTH[0]
I
External interrupt request/input port H
9
IRQ1/IRL1/PTH[1]
I
External interrupt request/input port H
10
IRQ2/IRL2/PTH[2]
I
External interrupt request/input port H
11
IRQ3/IRL3/PTH[3]
I
External interrupt request/input port H
12
IRQ4/PTH[4]
I
External interrupt request/input port H
13
D31/PTB[7]
I/O
Data bus/I/O port B
14
D30/PTB[6]
I/O
Data bus/I/O port B
15
D29/PTB[5]
I/O
Data bus/I/O port B
16
D28/PTB[4]
I/O
Data bus/I/O port B
17
D27/PTB[3]
I/O
Data bus/I/O port B
18
D26/PTB[2]
I/O
Data bus/I/O port B
19
VssQ
-
Power for I/O (0V)
20
D25/PTB[1]
I/O
Data bus/I/O port B
21
VssQ
-
Power for I/O (3.3V)
22
D24/PTB[0]
I/O
Data bus/I/O port B
23
D23/PTA[7]
I/O
Data bus/I/O port A
24
D22/PTA[6]
I/O
Data bus/I/O port A
25
D21/PTA[5]
I/O
Data bus/I/O port A
26
D20/PTA[4]
I/O
Data bus/I/O port A
103
KX-TDA100DUP
27
Vss
-
Power supply (0V)
-
Vss
-
Power supply (0V)
28
D19/PTA[3]
I/O
Data bus/I/O port A
29
Vcc
-
Power supply (*3)
-
Vcc
-
Power supply (*3)
30
D18/PTA[2]
I/O
Data bus/I/O port A
31
D17/PTA[1]
I/O
Data bus/I/O port A
32
D16/PTA[0]
I/O
Data bus/I/O port A
33
VssQ
-
Power for I/O (0V)
34
D15
I/O
Data bus
35
VccQ
-
Power for I/O (3.3V)
36
D14
I/O
Data bus
37
D13
I/O
Data bus
38
D12
I/O
Data bus
39
D11
I/O
Data bus
40
D10
I/O
Data bus
41
D9
I/O
Data bus
42
D8
I/O
Data bus
43
D7
I/O
Data bus
44
D6
I/O
Data bus
45
VssQ
-
Power for I/O (0V)
46
D5
I/O
Data bus
47
VccQ
-
Power for I/O (3.3V)
48
D4
I/O
Data bus
49
D3
I/O
Data bus
50
D2
I/O
Data bus
51
D1
I/O
Data bus
52
D0
I/O
Data bus
53
A0
O
Address bus
54
A1
O
Address bus
55
A2
O
Address bus
56
A3
O
Address bus
57
VssQ
-
Power for I/O (0V)
58
A4
O
Address bus
59
VssQ
-
Power for I/O (3.3V)
60
A5
O
Address bus
61
A6
O
Address bus
62
A7
O
Address bus
63
A8
O
Address bus
64
A9
O
Address bus
65
A10
O
Address bus
66
A11
O
Address bus
67
A12
O
Address bus
68
A13
O
Address bus
69
VssQ
-
Power for I/O (0V)
70
A14
O
Address bus
71
VccQ
-
Power for I/O (3.3V)
72
A15
O
Address bus
73
A16
O
Address bus
74
A17
O
Address bus
75
A18
O
Address bus
76
A19
O
Address bus
77
A20
O
Address bus
78
A21
O
Address bus
79
Vss
-
Power supply (0V)
-
Vss
O
Power supply (0V)
80
A22
O
Address bus
81
Vss
-
Power supply (*3)
-
Vss
-
Power supply (*3)
82
A23
O
Address bus
83
VssQ
-
Power for I/O (0V)
84
A24
O
Address bus
85
VssQ
-
Power for I/O (3.3V)
86
A25
O
Address bus
87
BS/PTK[4]
O/I/O
Bus cycle start signal/I/O port K
88
RD
O
Read stroke
89
WE0/DQMLL
O
D7-D0 select signal/DOM (SDRAM)
Pin No.
Pin Name
I/O
Description
104
KX-TDA100DUP
90
WE1/DQMLU/WE
O
D15-D8 select signal/DOM (SDRAM)
91
WE2/DQMUL/ICIORD/
PTK[6]
PTK[6]
O/I/O
D23-D16 select signal/DOM (SDRAM) /PCMCIA I/O read/I/O port K
92
WE3/DQMUU/
ICIOWR/PTK[7]
ICIOWR/PTK[7]
O/I/O
D31-D24 select signal/DOM (SDRAM) /PCMCIA I/O write/I/O port K
93
RD/WR
O
Read/Write
94
AUDSYNC/PTE[7]
O/I/O
AUD synchronization/I/O port E
95
VssQ
-
Power for I/O (0V)
96
CS0/MCS[0]
O
Chip select 0/mask ROM chip select 0
97
VccQ
-
Power for I/O (3.3V)
98
CS2/PTK[0]
O/I/O
Chip select 2/I/O port K
99
CS3/PTK[1]
O/I/O
Chip select 3/I/O port K
100
CS4/PTK[2]
O/I/O
Chip select 4/I/O port K
101
CS5/PTK[3]
O/I/O
Chip select 5/CE1 (Area 5PCMCIA)/I/O port K
102
CS6/CE1B
O
Chip select 6/CE1 (Area 6PCMCIA)
103
CE2A/PTE[4]
O/I/O
CE2(Area 5PCMCIA)/ I/O port K
104
CE2B/PTE[5]
O/I/O
CE2(Area 6PCMCIA)/ I/O port K
105
CKE/PTK[5]
O/I/O
CK Enable (SDRAM) / I/O port K
106
RAS3L/PTJ[0]
O/I/O
RAS for low 32M/64M bytes address (SDRAM) /I/O port J
107
PTJ[1]
I/O
I/O port J
108
CASL/PTJ[2]
O/I/O
RAS for low 32M/64M bytes address (SDRAM) /I/O port J
109
VssQ
-
Power for I/O (0V)
110
CASU/PTJ[3]
O/I/O
RAS for low 32M bytes address (SDRAM) /I/O port J
111
VssQ
-
Power for I/O (3.3V)
112
PTJ[4]
I/O
I/O port J
113
PTJ[5]
I/O
I/O port J
114
DACK0/PTD[5]
O/I/O
DMA acknowledge0/I/O port D
115
DACK1/PTD[7]
O/I/O
DMA acknowledge1/I/O port D
116
PTE[6}
I/O
I/O port E
117
PTE[3}
I/O
I/O port E
118
RAS3U/PTE[2]
O/I/O
RAS for low 32M bytes address (SDRAM) / I/O port E
119
PTE[1]
I/O
I/O port E
120
TDO/PTE[0]
O/I/O
Test data output/I/O port E
121
BACK
O
Bus acknowledge
122
BREQ
I
Bus request
123
WAIT
I
Hardware wait request
124
RESETM
I
Manual reset request
125
ADTRG/PTH[2]
I
Analog trigger/input port H
126
IOIS16/PTG[7]
I
IOIS168 (PCMCI) / I/O port G
127
ASEMD0/PTG[6]
I
ASE mode:4/I/O port G
128
ASEBRKAK/PTG[5]
I/O
ASE break acknowledge/I/O port G
129
PTG[4]/CKIO2
I/O
Input port G/clock output
130
AUDATA[3]/PTG[3]
I/O/I
AUD data/input port G
131
AUDATA[2]/PTG[2]
I/O/I
AUD data/input port G
132
Vss
-
Power supply (0V)
-
Vss
-
Power supply (0V)
133
AUDATA[1]/PTG[1]
I/O/I
AUD data/input port G
134
Vcc
-
Power supply (*3)
-
Vcc
-
Power supply (*3)
135
AUDATA[0]/PTG[0]
I/O/I
AUD data/input port G
136
TRST/PTF[7]/PINT[15] I
Test reset/input port F/port interruption
137
TMS/PTF[6]/PINT[14] I
Test mode switch/input port F/port interruption
138
TDI/PTF[5]/PINT[13]
I
Test mode switch/input port F/port interruption
139
TCK/PTF[4]/PINT[12]
I
Test clock/input port F/port interruption
140
IRS3/PTF[3]/PINT[11] I
External interrupt request/input port F/port interruption
141
IRS2/PTF[2]/PINT[10] I
External interrupt request/input port F/port interruption
142
IRS1/PTF[1]/PINT[9]
I
External interrupt request/input port F/port interruption
143
IRS0/PTF[0]/PINT[8]
I
External interrupt request/input port F/port interruption
144
MD0
I
Clock mode setting
145
Vcc-PLL1*2
-
Power for PLL1 (*3)
146
CAP1
-
External capacity terminal for PLL1
147
Vss-PLL1*2
-
Power for PLL1 (0V)
148
Vss-PLL2*2
-
Power for PLL1 (1V)
149
CAP2
-
External capacity terminal for PLL2
150
Vcc-PLL2*2
-
Power for PLL2 (*3)
151
AUDCK/PTH[6]
I
AUD clock/input port H
152
Vss
-
Power supply (0V)
Pin No.
Pin Name
I/O
Description
Click on the first or last page to see other KX-TDA100DUP service manuals if exist.