Panasonic KX-TDA100DUP (serv.man3) Service Manual / Supplement ▷ View online
3
KX-TDA100DUP
1.3.
Specifications
Change from the Original Service Manual Section 17.1.
Functional Block
Functional contents
Extension Interface
Number of Ports
24 ports
SLT Interface
-26V 26mA Feeding function
Dial-pulse signal detecting function
DTMF signal detecting function
Bell signal issuing function
Hook detecting function
Ringtrip detecting function
2W/4W converting function
Surge protective function
Message Waiting sending function
CODEC function
Dial-pulse signal detecting function
DTMF signal detecting function
Bell signal issuing function
Hook detecting function
Ringtrip detecting function
2W/4W converting function
Surge protective function
Message Waiting sending function
CODEC function
• Test function (Loop back, Tone generation)
• Programmable digital filtering function
• Serial interface function
• PIO function
• Programmable digital filtering function
• Serial interface function
• PIO function
DTMF Receiver
24 lines for each port
Caller ID (FSK)
24 lines for each port
On-board Ringer
20/25Hz 65Vrms
Phase control (Three-phase / Four-phase)
Phase control (Three-phase / Four-phase)
On-board DC/DC Power Supply
Input +15V
Output +3.3V
Input +40V
Output : VBAT(The required negative battery voltage).
The battery voltage generation circuit intelligently tracks the VBAT voltage to the optimal value under each
operating state (e.g. on-hook, off-hook, ringing, etc.)
Output +3.3V
Input +40V
Output : VBAT(The required negative battery voltage).
The battery voltage generation circuit intelligently tracks the VBAT voltage to the optimal value under each
operating state (e.g. on-hook, off-hook, ringing, etc.)
Power Failure Forwarding Function
2 lines supported
ASIC
EC bus interface function
H.100 bus interface function, Digital PLL function
Local bus interface function
Time switch function, Gain controlling function, FIFO/DPRAM function
Intelligent PIO function
H.100 bus interface function, Digital PLL function
Local bus interface function
Time switch function, Gain controlling function, FIFO/DPRAM function
Intelligent PIO function
Control Unit
CPU
SH-1/SH7020 (12.288MHz)
Flash ROM
512Kbyte
SRAM
128Kbyte
PLD
• Interface between codec and CPU
• Lattice MachX02 LCMXO2-640HC-4TG100C
• Lattice MachX02 LCMXO2-640HC-4TG100C
LED Display Circuit
Card status indicating LED: Two colors (Red/Green)
External Interface Connector
Extension interface
50pin Amphenol connector: 1
Power failure forwarding 4pin modular jack: 1
4
KX-TDA100DUP
1.4.
Technical Descriptions
Change from the Original Service Manual Section 17.3.
1.4.1.
Block Diagram
MCSLC24 BLOCK DIAGRAM
PLD
TACKER/
SAMSON
Backboard
BB Connector
OSC16.3 8
4 M
OSC
12.288M
EC-Bus
CT-Bus
15V
Card_ID
FLASH
(512KB)
SRAM
(128KB)
PCM-HW
Serge
PFT
Jack
T/R
PFT
Relay
T/R
SLIC/CODEC
2ch
Port1
SCI(7pin)
DC/DC
3.3V
FPGA_INT
BELL_SYNC
nHALT
nIRQ1
BELL_SYNC
FPGA_INT
Diag T/R
nHALT
40V
Si32261
Diag
Diag T/R
nCS0
nCS1
nCS2
nCS3
nCS[3: 0]
nIRQ1
CPU
nIRQ0
nIRQ1
nIRQ3
Port4
Port3
Port2
Port6
Port5
PFT
Relay
Port7
8
Port 23 24
Port 21 22
Port 19 20
Port 17 18
Port 15 16
Port 13 14
Port 11 12
Port 9
10
Si32261
Si32261
SPI
C_CS[0:11]
C_INT[0:11]
nIRQ2
Local
Control
Bus
Control
Bus
C_CS[0]
C_CS[1]
C_CS[2]
C _INT[0]
C_INT[1]
C_INT[2]
C_INT[3]
C_CS[3]
PCM_HW
SPI
C_INT[4]
C_CS[4]
PCM_HW
SPI
C_INT[5]
C_CS[5]
PCM_HW
SPI
C_INT[6]
C_CS[6]
PCM_HW
SPI
C_INT[7]
C_CS[7]
PCM_HW
SPI
C_INT[8]
C_CS[8]
PCM_HW
SPI
C_INT[9]
C_CS[9]
PCM_HW
SPI
C_INT[10]
C_CS[10]
PCM_HW
SPI
C_INT[11]
C_CS[11]
PCM_HW
SPI
Port8
Port7
Port10
Port9
Port12
Port11
Port14
Port13
Port16
Port15
Port18
Port17
Port20
Port19
Port22
Port21
Port24
Port23
Backboard
Con.
OSC32M
Program
connector
Note1.Group of Signal lines
Local Control
Local Control
Bus
:
connect to PLD
ADR[4:0],DATA[15:0], nWE , nR D ,nWAIT , CKIO
PCM - HW :
HWCLK
HWCLK
,HWFH
,DHW
,UHW
SPI :
SCLK
SCLK
,DOUT
,DIN
LED x 2
40V
Serge
DCDC
DCDC
40V
Relay
control
circuit
PR_SET
PF_RELAY
*1:These Blocks are not mounted on PCB.
PFT
Jack
Jack
Serge
PFT
Relay
PFT
DCDC
Serge
DCDC
Relay
T/R
T/R
*1
5
KX-TDA100DUP
1.4.2.
Circuit Operation
1.4.2.1.
Control-System Circuit
1.4.2.1.1.
CPU Peripherals
• CPU (System clock: 12.288 MHz)......IC601
Data bus: 16bit, Address bus: 23bit
• Flash ROM (512Kbyte)......IC602
Flash memory consists of two areas: boot space and administration space.
Administration program can be rewritten through downloading.
Administration program can be rewritten through downloading.
• SRAM (1Mbit)......IC603
Used for the data buffer for CPU work area, and SLT communication.
• Reset
Resets of an MCSLC24 card are roughly classified into the two kinds: ASIC reset and LPR reset.
After the release of the ASIC reset, the LPR reset is released by the soft reset from the side of the main card and the LPR pro-
gram is booted.
After the release of the ASIC reset, the LPR reset is released by the soft reset from the side of the main card and the LPR pro-
gram is booted.
Type of reset
Reset method
Specification
ASIC reset
ASIC reset is reset under the AND condition of reset signals (negative logic)
listed below.
listed below.
Power-on reset
Reset by reset IC
Hard reset from the main bus
Reset by EC_RST signal
Soft reset from the main bus
Released after the specified time
LPR reset
Soft reset from the main bus
Low active
Reset pulse width: 1.6 microseconds or more
Reset pulse width: 1.6 microseconds or more
6
KX-TDA100DUP
• LED Operation status indicating LED (Two colors)
OFF: Fault
Red ON: Fault (RESET included)
Green ON: Normal (Line not in use)
Green Flash (60/minute): Normal (Line in use)
Orange: OUS (Because OUS needs to be controlled by MPR, reset terminal and port control terminal are Red Blinking: OUS to
generate OUS)
Red ON: Fault (RESET included)
Green ON: Normal (Line not in use)
Green Flash (60/minute): Normal (Line in use)
Orange: OUS (Because OUS needs to be controlled by MPR, reset terminal and port control terminal are Red Blinking: OUS to
generate OUS)
• Instantaneous power interruption operation
When instantaneous power interruption is 300msec or less, reset operation is not carried out because the voltage is retained by
the capacitor in the power supply.
After HALT from MPR is detected at the DC power down port, CPU goes into the sleep mode by executing the instruction of
SLEEP.
At the sleep mode, the CPU/Clock enters the halt state while the contents of the register, the internal RAM, and the I/O port are
maintained.
When the instantaneous power interruption is released, HALT is negated, and CPU is recovered to the normal mode by the
detection of IRQ0=L
the capacitor in the power supply.
After HALT from MPR is detected at the DC power down port, CPU goes into the sleep mode by executing the instruction of
SLEEP.
At the sleep mode, the CPU/Clock enters the halt state while the contents of the register, the internal RAM, and the I/O port are
maintained.
When the instantaneous power interruption is released, HALT is negated, and CPU is recovered to the normal mode by the
detection of IRQ0=L