Panasonic KX-TDA0158CE Service Manual ▷ View online
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KX-TDA0158CE
4.2.3.
Line Interface
This circuit handles data communication from DHLC(DLC) card to CS. CS is connected to DHLC(DLC) card by 4 adjacent ports.
The signal from DHLC(DLC) card is provided to CN100, and provided to comparator (IC108-115) via filter and pulse transformer
(T100-103). These digital data is transferred to FPGA (IC103)
The signal from DHLC(DLC) card is provided to CN100, and provided to comparator (IC108-115) via filter and pulse transformer
(T100-103). These digital data is transferred to FPGA (IC103)
Note:
The GND of CS(KX-TDA0158CE) is not common to the GND of the PBX itself, care must be taken when using a measuring
device such as an oscilloscope. (Make sure to use the measuring device with its frame ground open.)
device such as an oscilloscope. (Make sure to use the measuring device with its frame ground open.)
SYNC (5bit)
:Synchronization bit
MAN (3bit)
:Frame header detection
Cch (1bit)
:Control channel
Dch (2bit)
:Data channel
B1ch, B2ch (8bit) :Bearer channel
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KX-TDA0158CE
4.2.4.
FPGA
FPGA (IC103) has the following features.
(1) Voice data transmission
Extracts voice data from digital data and provides to BBIC.
(2) Superframe detection, delay compensation
Detects super frame synchronization signal and compensates time difference of delay caused by the different cable length
(1) Voice data transmission
Extracts voice data from digital data and provides to BBIC.
(2) Superframe detection, delay compensation
Detects super frame synchronization signal and compensates time difference of delay caused by the different cable length
from DHLC(DLC) card, then provides to PSYNC pin of BBIC.
(3) Address decoder, internal registers
Address decoder to generate chip select signal for other ICs and internal registers to set FPGA operation.
Address decoder to generate chip select signal for other ICs and internal registers to set FPGA operation.
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KX-TDA0158CE
4.2.5.
RF Interface Circuit
Data signals for RF control and RX/TX data is connected between BBIC and RF module.
The modulated signal is provided to 2 antennas via CN104 and CN105.
The modulated signal is provided to 2 antennas via CN104 and CN105.
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KX-TDA0158CE
4.2.6.
Power Supply Circuit
5.5V, 1.8V, 3.2V, 1.2V, 2.5V, and 2.18V is generated in CS. 2.18V and 2.5V are the power supply for RF module.
3.2V is the power supply for logic circuit. 1.2V and 2.5V is used as the power supply of FPGA.
3.2V is the power supply for logic circuit. 1.2V and 2.5V is used as the power supply of FPGA.
(1) Input Filter, Rectifier Circuit
Input filter for noise rejection and rectifier circuit.
(2) DC/DC Converter Circuit
Generate 5.5V from DC40V power supply.
(3) Power Back up Circuit
All power supply is back- upped by secondary electric double layer capacitor.
Input filter for noise rejection and rectifier circuit.
(2) DC/DC Converter Circuit
Generate 5.5V from DC40V power supply.
(3) Power Back up Circuit
All power supply is back- upped by secondary electric double layer capacitor.
4.2.7.
Clock Circuit
2 type of clock are used in this CS.
(1) BBIC Clock
10.368MHz is used for BBIC clock. The frequency is calibrated by BBIC(IC100).
(2) FPGA Clock
16.384MHz crystal oscillator is used for FPGA(IC103).
(1) BBIC Clock
10.368MHz is used for BBIC clock. The frequency is calibrated by BBIC(IC100).
(2) FPGA Clock
16.384MHz crystal oscillator is used for FPGA(IC103).
4.2.8.
Reset Circuit
IC105(Reset IC) supplies power on reset signal to BBIC. Reset signal for FPGA is supplied from BBIC port.
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