DOWNLOAD Panasonic KX-TDA0156CE Service Manual ↓ Size: 1.7 MB | Pages: 54 in PDF or view online for FREE

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KX-TDA0156CE is the Cell Station (CS) for TDA series. CS converts voice data from PBX to radio signal and transmits to Porta-
ble Station (PS). Conversely CS converts radio signal from PS to voice data and transmits to PBX.

The IC100(SC14429) is CPU with BBIC and DSP and is manufactured by Sitel. This CPU has 16 bits data bus and  processes
control command from PBX and PS.
Application software is stored in 32Mbit Flash Memory (IC101). This Flash Memory is so called Dual Operation type Flash. It is
possible to write data onto this Flash Memory in active status so that this Flash Memory is used as EEPROM. The FLASH mem-
ory of this Dual Operation type is effective in preventing fatal destruction when remote uploading is failed. If the power failure
occurs during program uploading, the FLASH memory data is lost. However, this type of memory is recoverable.
Furthermore calibration data for RSSI measurement and clock is stored in the Flash Memory, too.
2Mbit SRAM(IC102) is used as the work area. CN101 is the communication port for service purpose. CN101 is connected to the
serial port of the CPU.
SW100 is 6bits DIP switch to set the operating modes of CS, site survey mode, program upload mode and so on.

This circuit handles data communication to CSIF card (KX-TDA0144/KX-TDA0143). CS is connected to CSIF card by 4 wires.
The power voltage of CS is DC 40V supplied from CSIF card by 4 wires. The analog signal for data transmission is transferred
via outside wires. Voice data, control data and superframe synchronisation signal for CS synchronisation is carried on this ana-
log signal.
The signal from CSIF card is provided to CN100, and provided to DNIC (IC106) via filters and pulse transformer (T100).
DNIC is the abbreviation of Digital Network IC. DNIC has 2 operating modes, namely master mode and slave mode. DNIC
works as slave in CS. DNIC extracts clocks ( 8kHz frame signal and 4MHz clock ) and digital data in ST-BUS format the analog
signal provided by PBX.
These clocks and digital data are transferred to FPGA(IC103).
This ST-BUS digital data contains data channel, control channel and voice channel.
The first 2bits of the data channel are the control data. Voice channel contains 4 ADPCM data. And superframe synchronization
signal is carried by HK bit of control channel.

The GND of CS(KX-TDA0156CE) is not common to the GND of the PBX itself, so care must be taken when using a measuring

device such as an oscilloscope.(Make sure to use the measuring device with its frame ground open.)

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FPGA (IC103) has the following features.

MPU i/f module has the address decoder and the data I/O control part, and controls the access between CPU and internal mod-
ule.

ST-BUS i/f module controls Serial communications with DNIC, extractes to D channel, C channel(HK bit), and B channel from
the serial data, and this block is distributed these datas to an internal each module.
Moreover, Dch, Cch, and Bch that come from an internal each module are united, and this module outputs it to DNIC by the ST-
BUS format.

Detects superframe synchronisation signal from HK bit in the ST-BUS digital data and compensates time difference of delay
caused by the different cable length from CSIF card, then provides it to PSYNC pin of BBIC(IC100).

HDLC is the abbreviation of High level Data Line Control, means a protocol for highly reliable data communication.
D channel data from ST-BUS i/f is transmitted to/from CPU through this module.

Extracts voice data from ST-BUS digital data and changes format to BBIC PCM format, then provides it to BBIC(IC100).

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SC14429 manufactured by Sitel.

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6.7V, 4.9V, PA_V3.3V, 3.2V, RF2.5V, RF1.8V, 1.8V and 1.5V are generated in CS. 
6.7V is output of DC/DC Convertor. Other power supplies except 3.2V and 1.8V, RF1.8V are made from 6.7V by each regura-
tors.
4.9V is the power supply of DNIC(IC106).
PA_V3.3V and RF2.5V, RF1.8V are the power supply for RF block.
3.2V is the power supply for logic circuit. 
1.8V is the power supply for BBIC(IC100).
1.5V is used as the power supply of FPGA(IC103) internal core.

Input filter for noise rejection and diode bridge for misconnection protection.

This circuit controls the DC/DC converter for prompt return from the power interruption start-up.
And when the power supply is low voltage, This circuit controls ON/OFF of the DC/DC converter by DIPSW(SW100)

Generate 6.7V from DC40V power supply.

All power supply is backed up by the electric double layer capacitor.

Three kinds of clock are used in CS.

10.368MHz crystal oscillator is used.

16.384MHz crystal oscillator is used. 

10.24MHz crystal oscillator is used.

The output signal of reset IC is generated with the detection of 6.7V power supply. 
BBIC reset signal(BB_RSTN) is made from reset IC output and the configuration completion status signal of FPGA.
FPGA is reset by the port output from BBIC(IC100).(F_RST)