Panasonic KX-TDA0143XJ / KX-TDA0143CE Service Manual / Supplement ▷ View online
13
KX-TDA0143XJ/KX-TDA0143CE
14
KX-TDA0143XJ/KX-TDA0143CE
15
KX-TDA0143XJ/KX-TDA0143CE
16
KX-TDA0143XJ/KX-TDA0143CE
1.5.
BLOCK DIAGRAM
Changed from the original service manual section 6.
nCP0(nCHS4)
LA[12:0]
LD[7:0]
nRD
nWR
nCSI
Flas
h
ROM
A[15:0]
D[7:0]
nRD
nWR
nWR
nRD
nRD
nCS
nCS
A[19:0]
A[16:0]
D[15:0]
D[7:0]
SH-1
XTAL
12.288MHz
nWR
nCS[7:0]
LD[7:0]
nCHS4,HWCLK[0:1],nFH
CDSTo[O:7]CDSTi[0:7]
BOARD
ID
2
nIRQ
L_nRST
nBUSY
nRESET
HWCLK0(nC4M)
LDHW[0]
LUHW[0]
RESET
IC
nRESET
+15V
nRESET
nIRQ1
nIRQ0
nWAIT
JUMPER
MODE[5:0]
16.384
MHz
PLLCLK
DNIC
+40V
Echo
LA[13:0]
nCS[7:0],nC6[5:0],nRST,MCLK,nAS,nRD,nWR
P20(A/nu)
P2[3:2]
P3[7:0] (POW[7:0])
nWAIT
PB13
PB3
nCS60,MCLK
nWR,nRST
LA[7:0]
CSMG2_D[7:0]
XTAL
10MHz
POWH A
POWL A
D1A
D2A
C2M
DSTI2
DSTO2
DSTI1
DSTO1
SF_MO
SYNCI1
A[5:0]
D
[7:1]
nRST
CSN
MCK
WRN
C4MN
CHS4N
nC4M ,nCHS4
DHW0
UHW0
nF0H
nC4M
CDSTo1
CDSToO
CDSTiO
CDSTo[O:7]
nF0
SOUT RIN
D[7:0]
nWR
nCS1
nCS0
nCS2
nCS62
R/nW
nCS
nFH
MCLK
nCS6
nCS6[5:0]
LA[12:15]
CDSTi1
CDSTo2
CDSTi[O:7]
nIRQ3
nIRQ4
nFH
SEL
RSB[7:0]
nDEL[7:0]
RSB
0
RSB
1
RxSB
A/nu
+40V
DECODER
JUMPER
nC4M
CT_C8_A
CT_FRAME_A
CT_NETREF
CT_D[7:0]
LDHW[1]
SIN
ROUT
P1[7:0] (nDEL[7:0])
DHW[0]
U
HW[0]
CK
SF
SF
SF
nIRQ6
TCLKD
IRQOUT
SYNCI2
P22
P23
nRES
LED_RED
LED_GREEN
LDHW1
MCLK
nDS
nDS
GEN
CPUCK
VREF
VREF-
HWCLK1(C2M)
1M
BUS
TRANSCEIVER
LAW
DNIC
+40V
POWH B
POWL B
D1B
D2B
RxSB
CDSTi1
CCLK_CSMG2
D0_RES
SO
DIN
CCLK
FPGA_PROG
DIN_CSMG2
CCLK_CSMG2
DIN_CSMG2
SI
nCS
MOSI
CSO_B
DNIC
+40V
POWH C
POWL C
D1C
D2C
DSTI2
DSTO2
DSTI1
DSTO1
SYNCI1
A[5:0]
DHWI0
DHWO0
DHWI2
CSN
MCK
WRN
C4MN
CHS4N
nFON
nC4M
CDSTo1
CDSTo2
RxSB
SYNCI2
LAW
DNIC
+40V
E
MI &
S
erg
e
P
rot
ect
ion
POWH D
POWL D
D1D
D2D
RxSB
CCLK_CSMG22
D0_RES
DIN
CCLK
FPGA_PROG
DIN_CSMG2
MOSI
CSO_B
Done
Done
nCS61,MCLK
nWR,nRST
LA[7:0]
CSMG2_D[7:0]
nC4M ,nCHS4
DHW0
UHW0
CDSTo2
CDSTi2
CDSTi3
RSB
3
A/nu
SF
LDHW1
CSMG2_DONE0
CSMG2_DONE0
SCK
PB1
DHWI0
DHWO0
DHWI2
CSMG2_D[7:0]
CSMG2_D[7:0]
Power
IC
Power
IC
Power
IC
nCS6
nRD
M[0:2]
VS[0:2]
JUMPER
M[0:2]
JUMPER
nHALT
+5V
10.24MHz Clock
Generator
for DNIC
Clock
DRIVER
DRIVER
+3.3V
+2.5V
+1.2V
+1.8V
+3.3V
RAM
BLOCK-D
BLOCK-C
Trans
former
Power
Control
Control
Power
former
Trans
Protection
Serge
EMI &
nFH,nC4M
10.24MHz
Power
Control
former
Trans
EMI &
Serge
Protection
CSIF BLOCK-1
nFH,nC4
10.24MHz
BLOCK-A
10.24MHz
nFH,nC4M
CSMG2
LPR
EC_STOP
EC_CLK
EC_AD[15:0]
EC_PAR
EC_FRAME
EC_TRDY
EC_BE[1:0]
EC_PERR
EC_INT
EC_IDSEL
nSYSTE_RST
P0[7:0]
Canceller
MT93L00
Supply
Power
nHALT
ASIC
POW[3]
POW[2]
CSIF BLOCK-2
BLOCK-B
Power
Control
POW[1]
Protection
Serge
EMI &
POW[0]
Backboard
10.24MHz
nFH,nC4
ROM
Flash
D[7:1]
VS[0:2]
CSMG2
RSB2
A[10:0]
former
Trans
KX-TDA0143XJ/KX-TDA0143CE (CSIF4) Block DiagramKX-TDA0143XJ/KX-TDA0143CE
(CSIF4)
B
lock
Diagram
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