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97

Note

Description

[1]

GPIO reset/deep sleep operation: After any reset is asserted or if the PXA270 processor is in deep sleep mode, 
these pins are configured as GPIO inputs by default. The input buffers for these pins are disabled to prevent cur-
rent drain and must be enabled prior to use by clearing the read disable hold bit, PSSR[RDH]. Until RDH is 
cleared, each pin is pulled high (Pu-1), pulled low (Pd-0), or floated (Hi-Z).

[2]

Crystal oscillator pins: These pins connect the external crystals to the on-chip oscillators and are not affected by 
either reset or sleep. For more information, see the “Clocks and Power” chapter in the Marue N® PXA27x Pro-
cessor Family Developer ‘s Manual.

[3]

GPIO sleep operation: During the transition into sleep mode, the configuration of these pins is determined by the 
corresponding GPIO setting. This pin is not driven during sleep if the direction of the pin is selected to be an 
input. If the direction of the pin is selected as an output, the value contained in the Power Manager GPIO Sleep-
State register (PGSR0/1/2/3) is driven out onto the pin and held while the PXA270 processor is in sleep mode.
Upon exit from sleep mode, GPIOs that are configured as outputs continue to hold the standby, sleep, or deep-
sleep state until software clears the peripheral control hold bit, PSSR[PH]. Software must clear this bit (by writing 
0b1 to it) after the peripherals have been fully configured, as described in Note[1], but before the process actu-
ally uses them.
GPIOs that are configured as inputs immediately after exiting sleep mode cannot be used until PSSR[RDH] is 
cleared.

[4]

Static memory control pins: During sleep mode, these pins can be programmed either to drive the value in the 
Power Manager GPIO Sleep-State register (PGSR0/1/2/3) or to be placed in a Hi-Z (undriven) state. To select 
the Hi-Z state, software must set PCFR[FS]. If FS is not set, these pins function as described in Note[3] during 
the transition to sleep mode.

[5]

PCMCIA control pins: During sleep mode, these pins can be programmed either to drive the value in the Power 
Manager GPIO Sleep-State register (PGSR0/1/2/3) or to be placed in a Hi-Z (undriven) state. To select the Hi-Z 
state, software must set PCFR[FP]. If FP is not set, these pins function as described in Note[3] during the transi-
tion to sleep mode.

[6] (reserved)
[7]

When the power manager overrides the GPIO alternate function, the Power Manager GPIO Sleep-State regis-
ters (PGSR0/1/2/3) and the PSSR[RDH] bit are ignored. Pullup and pulldown are disabled immediately after the 
power manager overrides the GPIO function.

[8]

Output functions during sleep mode

[9]

Pull-up always enabled

[10] (reserved)
[11]

Pins do not function during sleep mode if the OS timer is active

[12] Pins must be floated by software during sleep mode (floating does not happen automatically)
[13] (reserved)
[14] (reserved)
[15] The pin is three-stateable (Hi-Z) based on the value of PCFR[FS]. There is no PGSR0/1/2/3 setting associated 

with the pin because it is not a GPIO.

[16] PWR_EN goes high during reset, between the assertion of the reset pin and the de-assertion of internal reset 

within the PXA270 processor, after SYS_EN is driven high.

[17] GPIOs 114 and115: The alternate function configuration of these pins is ignored when either PUCR[USIM114] or 

PUCR[USIM115] bits are set. Setting these bits forces the USIM enable signal onto these GPIOs.

[18] When software sets the OSCC[PIO_EN] or OSCC[TOUT_EN] bits, then any GPIO alternate function setting 

applied to GPIO<9> or GPIO <10> is overridden with the CLK_PIO function on GPIO<9> and CLK_TOUT on 
GPIO<10>.

[19]

Type

Description

IC

CMOS input

OC

CMOS output

OCZ

CMOS output three-stateable

ICOCZ

CMOS bidirectional three-stateable

IA

Analog input

OA

Analog output

IAOA

Analog bidirectional

IAOAZ

Analog bidirectional - three-stateable

PS

Power supply

98

99

100

Note:

1. RTL (Retention Time Limited)

The “RTL” marking indicates that its Retention Time is
Limited.
When production is discontinued, this item will continue to
be available only for a specific period of time. 
This period of time depends on the type of item, and the
local laws governing parts and product retention.
At the end of this period, the item will no longer be avail-
able.

2. Important safety notice

Components identified by the   mark indicates special
characteristics important for safety. When replacing any
of these components, only use specified manufacture's
parts.

3. The S mark means the part is one of some identical parts.

For that reason, it may be different from the installed part.

4. ISO code (Example: ABS-94HB) of the remarks column

shows quality of the material and a flame resisting grade
about plastics.

5. RESISTORS & CAPACITORS

Unless otherwise specified;
All resistors are in ohms (

Ω), k=1000Ω, M=1000kΩ

All capacitors are in MICRO FARADS (

µF), p=µµF

*Type & Wattage of Resistor