Panasonic KX-NS5162XSX Service Manual ▷ View online
21
KX-NS5162X/KX-NS5162SX
11 Appendix Information of Schematic Diagram
Note:
1. DC voltage measurements are taken with an oscilloscope or a tester with a ground.
2. The schematic diagrams and circuit board may be modified at any time with the development of new technology.
2. The schematic diagrams and circuit board may be modified at any time with the development of new technology.
22
KX-NS5162X/KX-NS5162SX
12 Exploded View and Replacement Parts List
12.1. IC DATA
12.1.1.
IC100 (MISC PLD)
PIN NO
Pin Name
I/O
Function
1
L_NETREF_OUT
O
NETREF output
2
nCSI
I
CPU bus chip select
3
L_A11
I
CPU bus address
4
L_A10
I
CPU bus address
5
VCC
-
VCC
6
GND
-
GND
7
L_A9
I
CPU bus address
8
L_A8
I
CPU bus address
9
L_A7
I
CPU bus address
10
L_A6
I
CPU bus address
11
VCC
-
VCC
12
L_A5
I
CPU bus address
13
L_A4
I
CPU bus address
14
L_A3
I
CPU bus address
15
L_A2
I
CPU bus address
16
L_A1
I
CPU bus address
17
L_A0
I
CPU bus address
18
L_D7
I/O
CPU bus data
19
L_D6
I/O
CPU bus data
20
L_D5
I/O
CPU bus data
21
L_D4
I/O
CPU bus data
22
GND
-
GND
23
VCC
-
VCC
24
L_D3
I/O
CPU bus data
25
L_D2
I/O
CPU bus data
26
VCC
-
VCC
27
L_D1
I/O
CPU bus data
28
L_D0
I/O
CPU bus data
29
nREAD
I
CPU bus read
30
nWRITE
I
CPU bus write
31
HW_CLK5
I
High Way clock input
32
HW_FH5
I
frame sync input
33
GND
-
GND
34
LDHW3
I
DOWN High Way
35
HW_CLK4
I
High Way clock input
36
HW_FH4
I
frame sync input
37
LDHW4
I
DOWN High Way
38
GPIO0
I/O
GPIO#0
39
GPIO1
I/O
GPIO#1
40
GPIO2
I/O
GPIO#2
41
GPIO3
I/O
GPIO#3
42
GPIO4
I/O
GPIO#4
43
GPIO5
I/O
GPIO#5
44
GND
-
GND
45
GPIO6
I/O
GPIO#6
46
VCC
-
VCC
IC100
2
9
PB4C
30
PB4D
31
PB
6A
/MCLK/CCLK
3
2
PB
6
B/
S
O/
S
PI
S
O
33
GND3
34
PB
6
C/PCLKT
2
_0
35
PB
6
D/PCLKC
2
_0
3
6
PB10
A
3
7
PB10B
38
PB10C/PCLKT
2
_1
39
PB10D/PCLKC
2
_1
40
PB1
2A
41
PB1
2
B
4
2
PB1
2
C
43
PB1
2
D
44
GND4
45
PB14
A
4
6
V
CCIO
2
_
2
4
7
PB14B
54
PR7A
55
VCCIO1_1
56
GND5
57
PR6D
58
PR6C
59
PR6B
60
PR6A
61
NC2
62
PR5D/PCLKC1_0
63
PR5C/PCLKT1_0
64
PR5B
65
PR5A
66
PR3D
67
PR3C
68
PR3B
69
PR3A
70
PR2D
71
PR2C
72
GND6
7
9
GND
7
80
V
CCIO0_1
81
PT10D/PROGR
A
MN
8
2
PT10C/
J
T
A
GENB
83
PT10B
84
PT10
A
85
PT9D/
S
D
A
/PCLKC0_0
8
6
PT9C/
S
CL/PCLKT0_0
8
7
PT9B/PCLKC0_1
88
PT9
A
/PCLKT0_1
89
NC3
90
PT
7
D/TM
S
91
PT
7
C/TCK
9
2
GND8
93
V
CCIO0_
2
94
PT
7
B/TDI
95
PT
7A
/TDO
9
6
PT
6
D
9
7
PT
6
C
4 PL2D/PCLKC3_2
5 VCCIO3_1
6 GND1
7 PL3A
8 PL3B
9 PL3C
10 PL3D
11 NC1
12 PL5A/PCLKT3_1
13 PL5B/PCLKC3_1
14 PL5C
15 PL5D
16 PL6A
17 PL6B
18 PL6C
19 PL6D
20
PL7A/PCLKT3_0
21
PL7B/PCLKC3_0
22
GND2
26
V
CCIO
2
_1
27
PB4
A
/C
SS
PIN
2
8
PB4B
48
PB14C/
S
N
49
PB14D/
S
I/
S
IS
PI
50
V
CC1
51
PR7D
52
PR7C
53
PR7B
73
VCCIO1_2
74
PR2B
75
PR2A
76
PT11D/DONE
77
PT11C/INITN
7
8
PT11
A
98
PT
6
B
99
PT
6A
100
V
CC
2
1 PL2A
2 PL2B
3 PL2C/PCLKT3_2
23
VCCIO3_2
24
PL7C
25
PL7D
23
KX-NS5162X/KX-NS5162SX
47
GPIO7
I/O
GPIO#7
48
GPIO8
I/O
GPIO#8
49
GPIO9
I/O
GPIO#9
50
VCC
-
VCC
51
GPIO10
I/O
GPIO#10
52
L_NETREF_IN[0]
I
NETREF input #0
53
L_NETREF_IN[1]
I
NETREF input #1
54
L_NETREF_IN[2]
I
NETREF input #2
55
VCC
-
VCC
56
GND
-
GND
57
L_NETREF_IN[3]
I
NETREF input #3
58
CARD_ID0
I
CARD ID0
59
CARD_ID1
I
CARD ID1
60
CARD_ID2
I
CARD ID2
61
NC
-
no connect
62
CARD_ID3
I
CARD ID3
63
nINT_MISC[0]
I
IRQ device#0
64
nINT_MISC[1]
I
IRQ device#1
65
nINT_MISC[2]
I
IRQ device#2
66
nINT_MISC[3]
I
IRQ device#3
67
nINT_MISC[4]
I
IRQ device#4
68
nCS_MISC[0]
O
CPU bus chip select output
69
nCS_MISC[1]
O
CPU bus chip select output
70
nCS_MISC[2]
O
CPU bus chip select output
71
nCS_MISC[3]
O
CPU bus chip select output
72
GND
-
GND
73
VCC
-
VCC
74
nCS_MISC[4]
O
CPU bus chip select output
75
HWCLKFHO[1]
O
multi mode clock output
76
HWCLKFHO[6]
O
multi mode clock output
77
LDHW4_PLD
O
DOWN High Way
78
HWCLKFHO[0]
O
multi mode clock output
79
GND
-
GND
80
VCC
-
VCC
81
PROGRAMN/RESET
I
configuration indicator
82
JTAGENB
I
JTAG enable
83
nWAIT
O
CPU bus wait
84
nPLD_INT
O
IRQ output
85
HWCLKFHO[2]
O
multi mode clock output
86
HWCLKFHO[3]
O
multi mode clock output
87
HWCLKFHO[4]
O
multi mode clock output
88
HWCLKFHO[5]
O
multi mode clock output
89
NC
-
no connect
90
TMS
I
JTAG TMS
91
TCK
I
JTAG TCK
92
GND
-
GND
93
VCC
-
VCC
94
TDI
I
JTAG TDI
95
TDO
O
JTAG TDO
96
LDHW3_PLD_[0]
O
DOWN High Way
97
LDHW3_PLD[1] /GPIO[12]
I/O
multi mode GPIO
98
LDHW3_DSP / GPIO[13]
I/O
multi mode GPIO
99
nINT_MISC[5] / GPIO[11]
I/O
multi mode GPIO
100
VCC
-
VCC
PIN NO
Pin Name
I/O
Function
24
KX-NS5162X/KX-NS5162SX
12.2. Cabinet and Electrical Parts
1
The positioning boss of BRACKET
needs to fit into the hole of PCB.
E1
E2
Stick PROTECT SHEET (E2)
along the TOP and SIDE Line of
ZNR COVER (E1).
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