Panasonic KX-NS500UC (serv.man2) Service Manual ▷ View online
97
KX-NS500UC
15 Exploded View and Replacement Parts List
15.1. IC Date
15.1.1.
IC400
Pin No
Pin Name
I/O
Function
1
NCS_I
I
CPU bus chip select
2
LAB_I[0]
I
CPU bus address
3
LAB_I[1]
I
CPU bus address
4
LAB_I[2]
I
CPU bus address
5
VCC
-
VCC
6
GND
-
GND
7
LAC_I[1]
I
CPU bus address
8
LAC_I[0]
I
CPU bus address
9
LAD_I[7]
I
CPU bus address
10
LAD_I[6]
I
CPU bus address
11
VCC
-
VCC
12
LAD_I[5]
I
CPU bus address
13
LAD_I[4]
I
CPU bus address
14
LAD_I[3]
I
CPU bus address
15
LAD_I[2]
I
CPU bus address
16
LAD_I[1]
I
CPU bus address
17
LAD_I[0]
I
CPU bus address
18
LD_IO[7]
I/O
CPU bus data
19
LD_IO[6]
I/O
CPU bus data
20
LD_IO[5]
I/O
CPU bus data
21
LD_IO[4]
I/O
CPU bus data
22
GND
-
GND
23
VCC
-
VCC
24
LD_IO[3]
I/O
CPU bus data
25
LD_IO[2]
I/O
CPU bus data
26
VCC
-
VCC
27
LD_IO[1]
I/O
CPU bus data
28
LD_IO[0]
I/O
CPU bus data
29
NRD_I
I
CPU bus read
30
NWR_I
I
CPU bus write
31
CK4M_I
I
High Way clock(4M)
32
HW8K_I
I
frame sync input
33
GND
-
GND
34
HWDI_I
I
DOWN High Way
35
HWCK_O
O
High Way clock to DSP
36
HWFH_O
O
frmae sync to DSP
37
HWDO_O
O
DOWN High Way to DSP
38
NRST_DSP_O
O
DSP reset
39
RVRS_I[0]
I
CO#0 reverse(reserved)
40
BELL_I[0]
I
CO#0 bell(reserved)
41
FAN_ALRM
-
FAN alarm(reserved)
42
RVRS_I[1]
I
CO#1 reverse(reserved)
43
BELL_I[1]
I
CO#1 bell(reserved)
44
GND
-
GND
45
SYSCK
O
no connect
IC400
CO_PLD
29
nRE
A
D
30
nWRITE
31
CLKIN
32
FHIN
33
GND3
34
D
A
T
A
IN
35
CLKOUT
36
FHOUT
37
D
A
T
A
OUT
38
NR
S
T_D
S
P
39
RE
V
ER
S
E0
40
BELL0
41
F
A
N_
A
LM
42
RE
V
ER
S
E1
43
BELL1
44
GND4
45
SYS
CKOUT
46
V
CC
47
RE
V
ER
S
E
2
54
REVERSE4
55
VCC
56
GND5
57
BELL4
58
CARD_EID3
59
REVERSE5
60
BELL5
61
NC2
62
nCS_EXT_OP0
63
nCS_EXT_OP1
64
CARD_ID0
65
CARD_ID1
66
CARD_ID2
67
CARD_ID3
68
CARD_EID0
69
DATA_DIR_CO
70
DATA_DIR_EXT
71
DSPG_ACK0
72
GND6
79
GND
7
80
V
CC
81
PROGR
A
MN
82
JT
A
GENB
83
nC
S
_E
X
T_B
AS
E
84
nW
A
IT
85
nPLD_INT
86
nC
S
_D
S
PG0
87
nC
S
_D
S
PG1
88
nC
S
_D
S
PG
2
89
NC3
90
TM
S
91
TCK
92
GND8
93
V
CC
94
TDI
95
TDO
96
D
S
PG_INT1
97
D
S
PG_INT
2
4
A22
5
VCC
6
GND1
7
A9
8
A8
9
A7
10
A6
11
VCC
12
A5
13
A4
14
A3
15
A2
16
A1
17
A0
18
D7
19
D6
20
D5
21
D4
22
GND2
26
V
CC
27
D1
28
D0
48
BELL
2
49
C
A
RD_EID1
50
V
CC
51
REVERSE3
52
BELL3
53
CARD_EID2
73
VCC
74
DSPG_ACK1
75
DSPG_ACK2
76
D
S
PG_INT0
77
nC
S
_CO_B
AS
E
78
nC
S
I
98
nC
S
_CO_OP0
99
nC
S
_CO_OP1
100
V
CC
1
nCS_BASE
2
A20
3
A21
23
VCC
24
D3
25
D2
98
KX-NS500UC
46
VCC
-
VCC
47
RVRS_I[2]
I
CO#2 reverse(reserved)
48
BELL_I[2]
I
CO#2 bell(reserved)
49
CARDEID_I[1]
I
enhanced CARD_ID
50
VCC
-
VCC
51
RVRS_I[3]
I
CO#3 reverse(reserved)
52
BELL_I[3]
I
CO#3 bell(reserved)
53
CARDEID_I[2]
I
enhanced CARD_ID
54
RVRS_I[4]
I
CO#4 reverse(reserved)
55
VCC
-
VCC
56
GND
-
GND
57
BELL_I[4]
I
CO#4 bell(reserved)
58
CARDEID_I[3]
I
enhanced CARD_ID
59
RVRS_I[5]
I
CO#5 reverse(reserved)
60
BELL_I[5]
I
CO#5 bell(reserved)
61
NC
-
no connect
62
NCS_EXT_O[1]
O
CPU chip select for EXT OP#0
63
NCS_EXT_O[2]
O
CPU chip select for EXT OP#0
64
CARDID_I[0]
I
CARD_ID
65
CARDID_I[1]
I
CARD_ID
66
CARDID_I[2]
I
CARD_ID
67
CARDID_I[3]
I
CARD_ID
68
CARDEID_I[0]
I
enhanced CARD_ID
69
DIR_COT_O
O
CPU bus direction control
70
DIR_EXT_O
O
CPU bus direction control
71
NINT_EXT_I[3]
I
acknowledge of DSP#0
72
GND
-
GND
73
VCC
-
VCC
74
NINT_EXT_I[4]
I
acknowledge of DSP#1
75
NINT_EXT_I[5]
I
acknowledge of DSP#2
76
NINT_EXT_I[0]
I
IRQ of DSP#0
77
NCS_COT_O[0]
O
CPU bus chip select for CO PLD
78
NCS_PLD_I
I
CPU bus chip select input(local)
79
GND
-
GND
80
VCC
-
VCC
81
PROGRAMN
I
configuration indicator
82
JTAGENB
I
JTAG enable
83
NCS_EXT_O[0]
O
CPU bus chip select for EXT PLD
84
NWAIT_O
O
CPU bus wait
85
NINT_O
O
IRQ output
86
NCS_DSP_O[0]
O
CPU bus chip select for DSP#0
87
NCS_DSP_O[1]
O
CPU bus chip select for DSP#1
88
NCS_DSP_O[2]
O
CPU bus chip select for DSP#2
89
NC
-
no connect
90
TMS
-
JTAG TMS
91
TCK
-
JTAG TCK
92
GND
-
GND
93
VCC
-
VCC
94
TDI
-
JTAG TDI
95
TDO
-
JTAG TDO
96
NINT_EXT_I[1]
I
IRQ of DSP#1
97
NINT_EXT_I[2]
I
IRQ of DSP#2
98
NCS_COT_O[1]
O
CPU bus chip select for CO OP#0
99
NCS_COT_O[2]
O
CPU bus chip select for CO OP#1
100
VCC
-
VCC
Pin No
Pin Name
I/O
Function
99
KX-NS500UC
15.1.2.
IC401
Pin No
Pin Name
I/O
Function
1
NIRQ_O[1]
O
IRQ outout
2
HW4M_I
I
High Way clock input
3
HW8K_I
I
frame sync input
4
HWDI_I
I
DOWN High Way
5
VCC
-
VCC
6
GND
-
GND
7
NCS_I
I
CPU bus chip select
8
NIRQ_EX_I[0]
I
IRQ input from CO_PLD
9
RST_CO_O
O
reset output(reserved)
10
LA_I[6]
I
CPU bus address
11
VCC
-
VCC
12
LA_I[5]
I
CPU bus address
13
LA_I[4]
I
CPU bus address
14
LA_I[3]
I
CPU bus address
15
LA_I[2]
I
CPU bus address
16
LA_I[1]
I
CPU bus address
17
LA_I[0]
I
CPU bus address
18
LD_IO[7]
I/O
CPU bus data
19
LD_IO[6]
I/O
CPU bus data
20
LD_IO[5]
I/O
CPU bus data
21
LD_IO[4]
I/O
CPU bus data
22
GND
-
GND
23
VCC
-
VCC
24
LD_IO[3]
I/O
CPU bus data
25
LD_IO[2]
I/O
CPU bus data
26
VCC
-
VCC
27
LD_IO[1]
I/O
CPU bus data
28
LD_IO[0]
I/O
CPU bus data
29
NIRQ_EX_I[3]
I
IRQ from CO OPTIN#0
30
NIRQ_EX_I[4]
I
IRQ from CO OPTIN#1
31
RST_EX_O[2]
O
CO OPTION#0 reset
32
RST_EX_O[3]
O
CO OPTION#1 reset
33
GND
-
GND
34
CNT_DLC_O[0]
O
DPT#0 power control
35
CNT_DLC_O[1]
O
DPT#0 power control
36
CNT_DLC_O[2]
O
DPT#1 power control
37
CNT_DLC_O[3]
O
DPT#1 power control
38
NC
-
no connection
39
CNT_RSYNC_O
O
ring sync output
40
NRST_SLIC
O
SLIC reset
41
SCLK[0]
O
SLIC control bus clock
42
S_CS[0]
O
SLIC control bus chip select
43
NIRQ_SL_I[0]
I
IRQ from SLIC#0
44
GND
-
GND
45
nHALT_O
O
LPR halt signal
46
VCC
-
VCC
47
S_CS[1]
O
SLIC control bus chip select
48
NIRQ_SL_I[1]
I
IRQ from SLIC#1
49
S_CS[2]
O
SLIC control bus chip select
IC401
EXT_PLD
29
nINT_CO0
30
nINT_CO1
31
nR
S
T_CO_OP0
32
nR
S
T_CO_OP1
33
GND3
34
POW
A
[0]
35
POW
A
[1]
36
POWB[0]
37
POWB[1]
38
PB10C/PCLKT
2_1
39
RING_
SY
NC
40
nR
S
T_E
X
T
41
S
LIC_CLK0
42
S
LIC_C
S
0
43
S
LIC_INT0
44
GND4
45
nH
A
LT
46
V
CC
47
S
LIC_C
S
1
54
SLIC_UD
55
VCC
56
GND5
57
SLIC_DD
58
CLKOUT
59
FHOUT
60
DATAOUT
61
NC2
62
SLIC_CLK1
63
SLIC_CS4
64
SLIC_INT4
65
SLIC_CS5
66
SLIC_INT5
67
SLIC_CS6
68
SLIC_INT6
69
SLIC_CS7
70
SLIC_INT7
71
nINT_EXT0
72
GND6
79
GND
7
80
V
CC
81
PROGR
A
MN
82
JT
A
GENB
83
C
A
RD_ID0
84
C
A
RD_ID1
85
C
A
RD_ID
2
86
C
A
RD_ID3
87
F
A
N_
A
LA
RM
88
nW
A
IT_IN
89
NC3
90
TM
S
91
TCK
92
GND8
93
V
CC
94
TDI
95
TDO
96
nRE
A
D
97
nWRITE
4
DATAIN
5
VCC
6
GND1
7
nCSI
8
nINT_BASECO
9
nRST_CO
10
A6
11
VCC
12
A5
13
A4
14
A3
15
A2
16
A1
17
A0
18
D7
19
D6
20
D5
21
D4
22
GND2
26
V
CC
27
D1
28
D0
48
S
LIC_INT1
49
S
LIC_C
S2
50
V
CC
51
SLIC_INT2
52
SLIC_CS3
53
SLIC_INT3
73
VCC
74
nINT_EXT1
75
nRST_EXT_OP0
76
nR
S
T_E
X
T_OP1
77
RL
Y
_S
ET
78
RL
Y
_RE
S
ET
98
nW
A
IT
99
nPLD_INT#0
100
V
CC
1
nPLD_INT#1
2
HWCLK
3
FHIN
23
VCC
24
D3
25
D2
100
KX-NS500UC
50
VCC
-
VCC
51
NIRQ_SL_I[2]
I
IRQ from SLIC#2
52
S_CS[3]
O
SLIC control bus chip select
53
NIRQ_SL_I[3]
I
IRQ from SLIC#3
54
SDI
I
SLIC control bus input
55
VCC
-
VCC
56
GND
-
GND
57
SDO
O
SLIC control bus output
58
HWCK_O
O
High Way clock to SLIC
59
HWFH_O
O
frame sync to SLIC
60
HWDO_O
O
DOWN High Way to SLIC
61
NC
-
no connection
62
SCLK[1]
O
SLIC control bus clock
63
S_CS[4]
O
SLIC control bus chip select
64
NIRQ_SL_I[4]
I
IRQ from SLIC#4
65
S_CS[5]
O
SLIC control bus chip select
66
NIRQ_SL_I[5]
I
IRQ from SLIC#5
67
S_CS[6]
O
SLIC control bus chip select
68
NIRQ_SL_I[6]
I
IRQ from SLIC#6
69
S_CS[7]
O
SLIC control bus chip select
70
NIRQ_SL_I[7]
I
IRQ from SLIC#7
71
NIRQ_EX_I[1]
I
IRQ from EXT OPTION#0
72
GND
-
GND
73
VCC
-
VCC
74
NIRQ_EX_I[2]
I
IRQ from EXT OPTION#1
75
RST_EX_O[0]
O
EXT OPTION#0 reset
76
RST_EX_O[1]
O
EXT OPTION#1 reset
77
CNT_PF_O[0]
O
PF relay set signal
78
CNT_PF_O[1]
O
PF relay reset signal
79
GND
-
GND
80
VCC
-
VCC
81
PROGRAMN
I
configuration indicator
82
JTAGENB
I
JTAG enable
83
CARDID_I[0]
I
BASE CARD CARD ID
84
CARDID_I[1]
I
BASE CARD CARD ID
85
CARDID_I[2]
I
BASE CARD CARD ID
86
CARDID_I[3]
I
BASE CARD CARD ID
87
FAN_STT_I
I
FAN alarm input
88
NWAIT_EX_I
I
CPU bus wait input
89
NC
-
no connection
90
TMS
I
JTAG_TMS
91
TCK
I
JTAG_TCK
92
GND
-
GND
93
VCC
-
VCC
94
TDI
I
JTAG_TDI
95
TDO
O
JTAG_TDO
96
NRD_I
I
CPU bus read
97
NWR_I
I
CPU bus write
98
NWAIT_O
O
CPU bus wait
99
NIRQ_O[0]
O
IRQ outout
100
VCC
-
VCC
Pin No
Pin Name
I/O
Function
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