DOWNLOAD Panasonic KX-NS500UC (serv.man2) Service Manual ↓ Size: 12.71 MB | Pages: 127 in PDF or view online for FREE

Model
KX-NS500UC (serv.man2)
Pages
127
Size
12.71 MB
Type
PDF
Document
Service Manual
Brand
Device
PBX / HYBRID IP-PBX
File
kx-ns500uc-sm2.pdf
Date

Panasonic KX-NS500UC (serv.man2) Service Manual ▷ View online

9
KX-NS500UC
4.2.
Main Unit
The Main Unit is constructed by CPU Board (MPR)  and Mother Board. The block diagram and operation of each card are
described here.
4.2.1.
CPU Board (MPR) 
Fig.2 shows detail block diagram of CPU Board (MPR) , and each function of CPU Board (MPR) is described in Table.4.
Table.4 CPU Board (MPR) Function Description
Device/Function Block
Description
CPU
CPU controls exchange and monitoring functions of the whole NS500 system.
DDR3
DDR3 is main memory of CPU Board (MPR). Operating system, application program and concerning data are
stored in this memory.
NAND Flash
Program and system data are stored in this memory.
SRAM
SRAM is backed up by battery, and system information is stored this non-volatilized memory.
FPGA
FPGA provides basic PBX function such as time switch, tone generation and so on.
USB
USB master port for maintenance.
L2SW/LAN(RJ45)
LAN port is used for VoIP and Web-MC connection.
SD Card
UM voice data are stored in this SD card.
RTC
RTC is battery backed up clock which maintains system clock of NS500 system.
ARM
Cortex- A8
600MHz
L1 32K/32K w/SED
L2 256K w/ECC
176K ROM 64K RAM
64K RAM
Crypto
DDR
Interface
DDR3
512MB
NAND
NAND
FLASH
1GB
UART
McASP
Ethernet
USB
SD
GPIO
Interrupt
etc.
DC/DC(+3.3V,+1.8V,+1.1V)
I2C
AC_ALM, DC_ALM,System Reset, FPGA_REBOOT, DONE
EXP-M
Connector
DSP
op
tio
n
Con
nec
tor
RMT
O
pti
on
Con
nec
tor
Master
FPGA
USB
TypeA
LAN
RJ45
RMII
USB- Host- I/F
SRAM
512KB
LED
RTC
+5V
External bus
ER,DR
SLID
E
S
W
SD-I/F
80PIN
C
O
N
N
E
C
T
O
R
(C
P
U
In
terf
ace)
TDM
L2SW
PHY
ST
A
T
US
PBX
MO
D
E
PHY
PHY
DC/DC
+3.3V
+15V
8bit
8bit
16bit
SD-Card
Connector
16bit
+5V
+VBAT
Exp
ansion
bu
s
UART- I/F
+5V
Fig.2 CPU Board (MPR) Block Diagram
10
KX-NS500UC
4.2.2.
Main Unit Mother Board
Fig.3 shows detail block diagram of Mother Board, and each function of Base is described in Table.5.
Table.5 Main Unit Mother Board Function Description
4.2.3.
SLIC/CODEC (SLC) Block
Refer to Service Manual of KX-NS5173/KX-NS5174.
4.2.4.
DSP (LCOT) Block
Refer to Service Manual of KX-NS5180.
4.2.5.
DPT I/F Block
Refer to Service Manual of KX-NS5170/KX-NS5171/KX-NS5172.
Device/Function Block
Description
PLD1(EXT_PLD)
PLD1 controls and monitors SLIC/CODEC LSI of each analog line port.
PLD2(CO_PLD)
PLD2 controls the trunk controller DSP which is used in each analog trunk port.
SLIC/CODEC
SLIC/CODEC is exclusive LSI which is used for analog line interface.
  1) Line interface power supply
  2) Dial pulse detection
  3) DTMF receiver / Caller ID generation
  4) Bell signal generation
  5) Hooking detection / Ringtrip detection
  6) 2W/4W conversion
  7) CODEC function
DSP(CO)
DSP(CO) is exclusive LSI which is used analog trunk port.
  1) Dial pulse generation
  2) DTMF signal generation / Caller ID detection
  3) Bell signal detection
  4) CPC signal detection
  5) 2W/4W conversion
  6) CODEC function
DPT I/F
DPT I/F is Digital Line Interface.
6
Trunk option
Connector
Extension option
Connector
80
P
IN
C
O
N
NE
C
T
O
R
(C
PU
In
te
rfa
ce)
RJ45
MOH
PAG
RJ45
RJ45
POWER I/F
Connector
Exp
ansi
on
 bu
s
SLIC/CODEC bus (SPI)
TDM Highway bus
AFE
DSP
(2ch)
AFE
AFE
SLIC/CODEC(2ch)
AFE
AFE
AFE
AFE
AFE
AFE
AFE
SLIC/CODEC(2ch)
SLIC/CODEC(2ch)
SLIC/CODEC(2ch)
SLIC/CODEC(2ch)
SLIC/CODEC(2ch)
SLIC/CODEC(2ch)
SLIC/CODEC(2ch)
DPT
I/F
(2ch)
DSP
(2ch)
ACALM, DCALM
+40V, GND
+15V, GND
Dial Pulse, CPC DET
Dial Pulse, CPC DET
RJ45
RJ45
RJ45
IIO bus
PLD1
( EXT_PLD)
DSP
(2ch)
AFE
Dial Pulse, CPC DET
DPT- I/F
FAN I/F
Connector
VBAT
+15V, GND
PLD2
(CO_PLD)
INT(2)
DC/DC
+3.3V, GND
15
12V
INT_SLIC
INT_DSP
INT
INT_EXT
INT_CO
FAN_ALM
RJ45
MOH
PAG
RJ45
MOH
PAG
CO1-CO2
CO2-CO3
CO4-CO5
Re
la
y
RJ45
SLT2
SLT1
Fig.3 Main Unit Mother Board Block Diagram
11
KX-NS500UC
4.3.
Expansion Unit
The expansion unit is constructed by CPU Board (SPR) and Mother Board. The block diagram and operation   of each card are
described here.
4.3.1.
CPU Board (SPR) 
Fig.4 shows detail block diagram of CPU Board (SPR), and each function of CPU Board (SPR) is described in Table.6.
Table.6 CPU Board (SPR) Function Description
Card
Description
CPU
CPU controls the line card in the expansion unit by the control from an CPU Board (MPR).
DDR3
DDR3 is main memory of CPU Board (SPR). Operating system, application program and concerning data are
stored in this memory.
NAND Flash
CPU program is stored in this memory.
FPGA
FPGA provides control and monitoring function of each line card.
ARM
Cortex- A8
300MHz
L1 32K/32K w/SED
L2 256K w/ECC
176K ROM 64K RAM
64K RAM
Crypto
DDR
Interface
DDR3
128MB
NAND
NAND
FLASH
256MB
UART
SD
GPIO
Interrupt
etc.
DC/DC(+3.3V,+1.8V,+1.1V)
AC_ALM, DC_ALM, System Reset, FPGA_REBOOT, DONE
Slave
FPGA
LED
+5V
External bus
80
P
IN
C
O
N
NE
C
T
O
R
(C
PU
In
te
rfa
ce)
S
T
A
TU
S
DC/DC
+3.3V
+15V
8bit
8bit
+5V
+VBAT
LVDS
Down
Highway
Up
Highway
FH+CLK
(8MHz)
Interrupt
Exp I/F
RJ45
NETREF
Exp
ansi
on
 bu
s
Fig.4 CPU Board (SPR) Block Diagram
12
KX-NS500UC
4.3.2.
Expansion Unit Mother Board
Fig.5 shows detail block diagram of Mother Board, and each function of Base is described in Table.7.
Table.7 Expansion Unit Mother Board Function Description
4.3.3.
SLIC/CODEC (SLC) Block
Refer to Service Manual of KX-NS5173/KX-NS5174.
Device/Function Block
Description
PLD1(EXT_PLD)
PLD1 controls and monitors SLIC/CODEC LSI of each analog line port.
SLIC/CODEC
SLIC/CODEC is exclusive LSI which is used for analog line interface.
    8) Line interface power supply
    9) Dial pulse detection
  10) DTMF receiver / Caller ID generation
  11) Bell signal generation
  12) Hooking detection / Ringtrip detection
  13) 2W/4W conversion
  14) CODEC function
Trunk option
Connector
Extension option
Connector
80PIN
CONN
ECT
OR
(CP
U
Int
er
fa
ce)
RJ45
POWER I/F
Connector
Exp
ansi
on
 bu
s
SLIC/CODEC bus (SPI)
TDM Highway bus
AFE
SLIC/CODEC(2ch)
AFE
AFE
AFE
AFE
AFE
AFE
AFE
SLIC/CODEC(2ch)
SLIC/CODEC(2ch)
SLIC/CODEC(2ch)
SLIC/CODEC(2ch)
SLIC/CODEC(2ch)
SLIC/CODEC(2ch)
SLIC/CODEC(2ch)
ACALM, DCALM
+40V, GND
+15V, GND
RJ45
RJ45
RJ45
PLD1
(EXT_PLD)
FAN I/F
Connector
+15V, GND
INT(2)
DC/DC
+3.3V, GND
15
12V
INT_SLIC
INT_EXT
INT_CO
FAN_ALM
RJ45
PFT
RJ45
PFT
PFT1-PFT2
PFT2-PFT3
SLT4
SLT3
Re
la
y
To SLT3-SLT4
PFT Relay
RJ45
SLT2
SLT1
Fig.5 Expansion Unit Mother Board Block Diagram
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