Panasonic KX-NS0154CE (serv.man2) Service Manual ▷ View online
5
KX-NS0154CE
3 Specifications
IP-CS Specification
RF Specification
CAUTION
• The IP-CS should be kept free of dust, moisture, high temperature (more than 40 C), low temperature (less than 0 C), and
vibration, and should not be exposed to direct sunlight.
• The IP-CS should not be placed outdoors (use indoors).
• The IP-CS should not be placed near high-voltage equipment.
• The IP-CS should not be placed on a metal object.
• The IP-CS should not be placed near high-voltage equipment.
• The IP-CS should not be placed on a metal object.
Items
Description
Type
4 channel CS
Supported Audio
Narrowband
Radio Method
DECT
VoIP Signalling Protocol
MGCP
IP Port Number Flexible Setting
Yes
Local Setting
Yes (through Web application)
Site Survey Mode
Yes (through Web application)
Initialisation
Yes (through Web application)
Maximum Simultaneous Calls
4 (8 with Activation key)
Power Supply
PoE
(IEEE 802.3af)
Optional AC adaptor
(KX-A239CE [PQLV206CE]/KX-A239UK [PQLV206E]/
KX-A239BX [PQLV206CE]/KX-A239EJ [PQLV206E]/
KX-A239AL [PQLV206AL])
VoIP Audio Codec
G.711, G.729A, G.726
LAN Port
10 BASE-T
100 BASE-TX
VLAN
Yes (802.1Q)
IP Addressing
DHCP
Static IP Address Setting
Software Upgrade
Yes
Built-in VPN
No
Weight
290 g
Size
(W) 190 mm x (H) 133.9 mm x (D) 39.3 mm
Items
Description
Radio Access Method
MultiCarrier TDMA-TDD
Frequency Band
1880 MHz to 1900 MHz
Number of Carriers
10
Carrier Spacing
1728 kHz
Transmission Output
Peak 250 mW
6
KX-NS0154CE
4 Technical Descriptions
4.1.
Block Diagram
3.
3V
1.
2V
RF
Cir
cuit
AN
T
AN
T
RX
_S
W
LNA
_I
NN
LNA
_I
N
TC_S
B
AL_O
UT
B
SL_O
UT
2
VCC_P
DQ
0~3
IC502 32
Mb
Q
SPI
Se
ria
l F
la
sh
3.
3V
S#
C
IC501 DCX
81
(Su
bD
SP)
RF
Q
SPI
IF
DCX
_B
O
O
T
S
YNC0
DV
F_RE
AD
DV
F_T
XRE
DCX
1_RE
A
DCX
1_T
XRE
S
PI
1_CS
S
P
I1_CL
SPI
_D
O
SPI
_D
I
DCX
1_R
TD
MA
_SC
TD
MA
_F
S
TDM
A_RX
TD
M
A_
T
UT
X
URX
X501
Se
ria
l T
est
Po
in
t
13.
824M
H
XI
N
XO
U
T
IC704
B
uffe
r
3.
3V
1.
2V
DQ
0~3
IC504 32
Mb
Q
SPI
Se
ria
l F
la
sh
3.
3V
S#
C
IC503 DCX
81
(Su
bD
SP)
Q
SPI
IF
DCX
_B
O
O
T
DV
F_RE
ADY
DV
F_T
XRE
Q
2
DCX
2_RE
AD
DCX
2_T
XRE
S
P
I2_CS
S
P
I2_CL
SPI
2_
D
S
P
I2_DI
DCX
1_RS
TD
MB_
SC
L
TD
MB_
FSY
N
C
TDM
B
_RX
TD
M
B
_TX
D
UT
X
URX
Se
ria
l T
est
P
oint
XI
N
TD
M
IF
SPI
IF
TD
M
IF
SPI
IF
XI
N
3.
3V
TD
M
IF
SPI
IF
TD
M
IF
SPI
IF
3.
3V
1.
2V
JT
AG
T
est
P
oint
JT
AG
T
est
P
oint
1.
8V
3.
3V
P
HY
_RS
MD
C
MD
IO
M
II_CO
L
M
II_RX
D
MI
I_
TX
C
MI
I_
TX
C
M
II_
TX
D0~3
MI
I_
TX
E
MI
I_
TX
E
M
II_RX
E
M
II_CRS
M
II_RX
D0~3
LI
NK
I2C_S
DA
IC302 PH
Y
I2C_CLK
XI
N
XO
U
T
X201
13.
824M
H
XI
N
IC301 PL
L
IC
13.
824M
H
25M
Hz
12M
Hz
3.
3V
T301 TR
AN
S
F
O
R
MER
P0
R
XP
P0
R
XN
P0
TX
N
P0
TX
P
LF
302
LF
301
JK3
02
LA
N
JA
C
K
D30
D30
IC303 Po
E
IC
1.
8V
MI
I I
F
UT
X
URX
Se
ria
l T
est
P
oint
TD
O,T
D
I,T
M
S
,
TCK
,RT
CK
TD
O,T
D
I,T
M
S
,
TCK
,RT
CK
JT
AG
T
est
P
oint
TD
O,T
D
I,T
M
S
,
TC
K
,RT
CK
VB
U
,U
S
B
P
,U
S
B
N
JK3
01
US
B
I2C_I
F
U
SB_
IF
IC102
1G
b
NA
ND
FL
AS
H
NF
LD0~7
NF
LRE
ADY
NF
LRD
NF
LW
R
NF
LCS
0
NF
LCLE
NF
LA
LE
FLA
S
H_I
3.
3V
LE
D
R
ESET
SW
D
IP
SW
IC101
1G
b
S
DRA
M
DDR_DA
0~1
DDR_DQ
0~1
DDR_CK
, DDR_/
CK
,
DDR_CK
E
,CCR_CS
0,
DDR_O
DT
,DDR_UDM
,
DDR_LDM
,DDR_/
W
E
,
DDR_/
CA
S
,DDR_/
RA
S
,
DDR_/
UDQ
S
,DDR_UDQ
S
,
DDR_/
LDQ
S
,DDR_LDQ
S
1.
8V
D101,
D102,
D10
SW
10
SW
30
JK7
01
DC
IC702
IC703
IC701
3.
3V
DC/
D
1.
8V
DC/
D
1.
2V
DC/
D
3.
3V
1.
8V
1.
2V
IC201
R
ESE
T
IC
IC100 DV
F9918
(C
PU
&D
SP)
JT
AG
_I
F
UA
RT
_I
F
JT
AG
_I
F
UA
RT
_I
F
JT
AG
_I
F
UA
RT
_I
F
7
KX-NS0154CE
4.2.
Main Processer
IC100 (DVF99) is main IC which controls almost IC's in this system.
And it has the acoustic echo canceller for 4 voice path.
IC503 (DCX81) is used for only echo canceller for another 4 voice path.
IC501 (DCX81) runs as DSP and RF circuit.
And it has the acoustic echo canceller for 4 voice path.
IC503 (DCX81) is used for only echo canceller for another 4 voice path.
IC501 (DCX81) runs as DSP and RF circuit.
4.3.
Power Supply Circuit
KX-NS0154 support 2 way power supply; AC adaptor and PoE (Power over Ethernet).
9V is supplied from AC adaptor through JK701.
48V is supplied from ethernet through JK302, and it is converted to 12V by IC303.
9V or 12V is converted 3.3V by IC702 (DCDC converter) and 1.8V by IC703 (DCDC converter).
IC701(Voltage regulator) regulates 1.2V from 1.8V.
9V is supplied from AC adaptor through JK701.
48V is supplied from ethernet through JK302, and it is converted to 12V by IC303.
9V or 12V is converted 3.3V by IC702 (DCDC converter) and 1.8V by IC703 (DCDC converter).
IC701(Voltage regulator) regulates 1.2V from 1.8V.
3.3V is used for Login and RF.
1.8V is used for DDR2 memory.
1.2V is used for core voltage of IC100, IC501 and IC503.
1.8V is used for DDR2 memory.
1.2V is used for core voltage of IC100, IC501 and IC503.
4.4.
Reset circuit
IC201 (Reset IC) detects supplied voltage from AC adaptor or PoE output, and it supplies Power-On-Reset signal to IC100
(DVF99).
IC100 supplies reset signal from GPIO to RSTN pin of IC501(DCX81 for RF) and IC503 (DCX81 for DSP).
Also IC100 supplies reset signal to IC302 (PHY).
(DVF99).
IC100 supplies reset signal from GPIO to RSTN pin of IC501(DCX81 for RF) and IC503 (DCX81 for DSP).
Also IC100 supplies reset signal to IC302 (PHY).
RF
IC501
DCX81
ARM
DSP
IC503
DCX81
ARM
DSP
Acoustic
Echo
Canceller
DSP
IC100 DVF99
ARM
Acoustic
Echo
Canceller
TDM
TDM
MII
1-4 path
5-8 path
8
KX-NS0154CE
4.5.
Clock Circuit
4.5.1.
System Clock
Main system clock (13.824MHz) is generated from X501, and Oscillation circuit consists of X501 and IC501.
This clock is used for basic clock of IC501's all internal clock and RF.
This clock is supplied to IC100 and IC503 via buffer IC (IC704).
This enables synchronization among IC100, IC501 and IC503.
X201 is used by IC100 during its boot sequence and basic clock for PLLIC (IC301).
This clock is used for basic clock of IC501's all internal clock and RF.
This clock is supplied to IC100 and IC503 via buffer IC (IC704).
This enables synchronization among IC100, IC501 and IC503.
X201 is used by IC100 during its boot sequence and basic clock for PLLIC (IC301).
4.5.2.
PLLIC
PLLIC (IC302) is controlled by IC100 with I2C bus.
PLLIC generate 12MHz and 25MHz clock.
12MHz is supplied to IC100 and used for USB circuit for maintenance.
25MHz is supplied to PHY for Ethernet communication.
PLLIC generate 12MHz and 25MHz clock.
12MHz is supplied to IC100 and used for USB circuit for maintenance.
25MHz is supplied to PHY for Ethernet communication.
4.6.
Memory Access Circuit
4.6.1.
IC100
IC100 (DVF99) has separated memory access port for NAND Flash memory (IC102) and DDR2 SDRAM (IC101).
The program for IC100 has been stored in IC102.
The program for IC100 has been stored in IC102.
4.6.2.
IC501 and IC503
IC501(DCX81 for RF) and IC503 (DCX81 for DSP) have the QSPI Serial Flash access port.
The program for IC501 has been stored in IC502, and the program for IC503 has been stored in IC504.
The program for IC501 has been stored in IC502, and the program for IC503 has been stored in IC504.
4.7.
Ethernet Circuit
Ethernet signals from JK302 are transfered to IC302(PHY) through T301.
IC302 transfers singal to DVF99(IC100)
IC302 transfers singal to DVF99(IC100)
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