DOWNLOAD Panasonic KX-NS0131X Service Manual ↓ Size: 1.91 MB | Pages: 55 in PDF or view online for FREE

Model
KX-NS0131X
Pages
55
Size
1.91 MB
Type
PDF
Document
Service Manual
Brand
Device
PBX / STACKING CARD FOR KX-NCP SERIES
File
kx-ns0131x.pdf
Date
PREV: Panasonic KX-NS0130X (serv.man2) Service Manual / Supplement

Panasonic KX-NS0131X Service Manual ▷ View online

45
KX-NS0131X
12.1.4. FPGA (IC501)
Pin No.
Pin Name
I/O
Discription Pin Usage
P1
IO_L83N_VREF_3 
O
Output for evaluation.
P2
IO_L83P_3 
O
Output for evaluation.
P3
GND Ground
P4
VCCO_3 
+3.3 Volt Power Supply
P5
IO_L52N_3 
I
Highway frame signal from STACK-M : SHW_NFH
P6
IO_L52P_3 
I
Highway clock from STACK-M : SHW_CLK
P7
IO_L51N_3 
I
Reset Input : NBSRSTOUT
P8
IO_L51P_3 
O
Output for evaluation.
P9
IO_L50N_3 
O
Output for evaluation.
P10
IO_L50P_3 
O
Output for evaluation.
P11
IO_L49N_3 
I
unused input (internal pull down)
P12
IO_L49P_3 
I
Input for evaluation.(internal pullup)
P13
GND Ground
P14
IO_L44N_GCLK20_3 
I
Write signal from CPU : L_NWE
P15
IO_L44P_GCLK21_3 I
unused 
input (internal pull down)
P16
IO_L43N_GCLK22_IRDY2_3 I
Input 
for evaluation.(internal pullup)
P17
IO_L43P_GCLK23_3 
I
Read signal from CPU : L_NRD
P18
VCCO_3 
+3.3 Volt Power Supply
P19
VCCINT 
+1.2 Volt Power Supply
P20
VCCAUX 
+3.3 Volt Power Supply
P21
IO_L42N_GCLK24_3 O
Indicates 
the 
shelf number to CPU : ESLFID[1]
P22
IO_L42P_GCLK25_TRDY2_3 I
Chip 
select to CircLink : NCS_CCLINK
P23
IO_L41N_GCLK26_3 
O
Output for evaluation.
P24
IO_L41P_GCLK27_3 
I
Indicates the shelf number from STACK-M : S_ESLFID[0]
P25
GND Ground
P26
IO_L37N_3 
O
Output for evaluation.
P27
IO_L37P_3 
I
CPU clock(65.536MHz) : CKIO_NEXUS
P28
VCCINT 
+1.2 Volt Power Supply
P29
IO_L36N_3 
I
Wait signal from the ASIC(IC101) : NWAIT_NEXUS
P30
IO_L36P_3 
O
Indicates the shelf number to CPU : ESLFID[0]
P31
VCCO_3 
+3.3 Volt Power Supply
P32
IO_L2N_3 
I
Ringer synchronous signal :S_RINGSYNC
P33
IO_L2P_3 
I
Input for evaluation.(internal pullup)
P34
IO_L1N_VREF_3 
O
Output for evaluation.
P35
IO_L1P_3 
I
unused input (internal pull down)
P36
VCCAUX 
+3.3 Volt Power Supply
P37
PROGRAM_B_2 
I
Start signal of FPGA configration : CPU_nRESET
P38
IO_L65N_CSO_B_2 
O
Chip select signal for Flash(4M bit) : NCS
P39
IO_L65P_INIT_B_2 
I
FPGA functional pin : INIT_B
P40
IO_L64N_D9_2 
I
Chip select signal for ASIC(IC101) : NCS5
P41
IO_L64P_D8_2 
I
Input for evaluation.(internal pullup)
P42
VCCO_2 
+3.3 Volt Power Supply
P43
IO_L62N_D6_2 
O
Write signal to CircLink : F nWR_CCLINK
P44
IO_L62P_D5_2 
I
Shelf FAN Alarm signal/CS delay measurement signal : nSLFFAN_ALM
P45
IO_L49N_D4_2 
I
CT Bus clock  : CT_C8
P46
IO_L49P_D3_2 
I
unused input (internal pull down)
P47
IO_L48N_RDWR_B_VREF_2 
I
unused input (internal pull down)
46
KX-NS0131X
P48
IO_L48P_D7_2 
I/O
CT Bus data:CT_D[7]
P49
GND Ground
P50
IO_L31N_GCLK30_D15_2 
I/O
CT Bus data:CT_D[6]
P51
IO_L31P_GCLK31_D14_2 
I/O
CT Bus data:CT_D[5]
P52
VCCINT 
+1.2 Volt Power Supply
P53
VCCAUX 
+3.3 Volt Power Supply
P54
GND Ground
P55
IO_L30N_GCLK0_USERCCLK_2 
I/O
CT Bus data:CT_D[4]
P56
IO_L30P_GCLK1_D13_2 
I
unused input (internal pull down)
P57
IO_L14N_D12_2 
I/O
CT Bus data:CT_D[3]
P58
IO_L14P_D11_2 
I/O
CT Bus data:CT_D[2]
P59
IO_L13N_D10_2 
I
unused input (internal pull down)
P60
IO_L13P_M1_2 
I
Configration Mode  : M1
P61
IO_L12N_D2_MISO3_2 
I/O
CT Bus data:CT_D[1]
P62
IO_L12P_D1_MISO2_2 
I/O
CT Bus data:CT_D[0]
P63
VCCO_2 
+3.3 Volt Power Supply
P64
IO_L3N_MOSI_CSI_B_MISO0_2 
O
serial i/f to Flash(4M bit) : SI
P65
IO_L3P_D0_DIN_MISO_MISO1_2 
I
serial i/f to Flash(4M bit) : SO
P66
IO_L2N_CMPMOSI_2 
I
CT Bus Frame signal :CT_FRAME
P67
IO_L2P_CMPCLK_2 
I
unused input (internal pull down)
P68
GND Ground
P69
IO_L1N_M0_CMPMISO_2 
I
Configration Mode  : M0
P70
IO_L1P_CCLK_2 O
serial 
i/f 
Clock to Flash(4M bit) : SCLK
P71
DONE_2 
O
Configuration completion signal (to Main) : DONE
P72
CMPCS_B_2 
I
FPGA functional pin connected High : CMPCS
P73
SUSPEND 
I
Suspended mode pin connected Low : SUSPEND
P74
IO_L74N_DOUT_BUSY_1 
I
unused input (internal pull down)
P75
IO_L74P_AWAKE_1 
I
unused input (internal pull down)
P76
VCCO_1 
+3.3 Volt Power Supply
P77
GND Ground
P78
IO_L47N_1 
O
Ringer signal generation timing to each line card : RING_SYNC_O
P79
IO_L47P_1 
O
FPGA Interrupt Signal out : FPGA_INT
P80
IO_L46N_1 
O
ready signal to CPU : CPU_NRDY
P81
IO_L46P_1 
I
FPGA Chip select from CPU : nCS_CTSW
P82
IO_L45N_1 
I
unused input (internal pull down)
P83
IO_L45P_1 
I
Write Enable signal from CPU : L_NWE0
P84
IO_L43N_GCLK4_1 
I
Read signal from CPU : nRD/nCAS
P85
IO_L43P_GCLK5_1 
I/O
LocalBus data :LD[5]
P86
VCCO_1 
+3.3 Volt Power Supply
P87
 IO_L42N_GCLK6_TRDY1_1 
I/O
LocalBus data :LD[6]
P88
IO_L42P_GCLK7_1 
I/O
LocalBus data :LD[3]
P89
VCCINT 
+1.2 Volt Power Supply
P90
VCCAUX 
+3.3 Volt Power Supply
P91
GND Ground
P92
IO_L41N_GCLK8_1 
I
LocalBus data :LD[0]
P93
IO_L41P_GCLK9_IRDY1_1 
I
unused input (internal pull down)
P94
IO_L40N_GCLK10_1 
I/O
LocalBus data :LD[1]
P95
IO_L40P_GCLK11_1 
I/O
LocalBus data :LD[2]
P96
GND Ground
P97
IO_L34N_1 
I/O
LocalBus data :LD[4]
P98
IO_L34P_1 
I/O
LocalBus data :LD[7]
P99
IO_L33N_1 
I
unused input (internal pull down)
P100
IO_L33P_1 I
Input 
for 
evaluation.(internal pullup)
P101
IO_L32N_1 
I
unused input (internal pull down)
P102
IO_L32P_1 
I
Register Address :A[0]
P103
VCCO_1 
+3.3 Volt Power Supply
P104
IO_L1N_VREF_1 
I
Register Address :LA[1]
P105
IO_L1P_1 
I
Register Address :LA[2]
P106
TDO 
(Open)
JTAG i/f pin(unused)
P107
TMS 
(Open)
JTAG i/f pin(unused)
P108
GND Ground
P109
TCK 
(Open)
JTAG i/f pin(unused)
P110
TDI 
(Open)
JTAG i/f pin(unused)
P111
IO_L66N_SCP0_0 
I
Register Address :LA[3]
P112
IO_L66P_SCP1_0 
I
Register Address :LA[4]
P113
GND Ground
P114
IO_L65N_SCP2_0 
I
Register Address :LA[5]
Pin No.
Pin Name
I/O
Discription Pin Usage
47
KX-NS0131X
P115
IO_L65P_SCP3_0 
I
Register Address :LA[6]
P116
IO_L64N_SCP4_0 
I
Register Address :LA[7]
P117
IO_L64P_SCP5_0 I
unused 
input (internal pull down)
P118
IO_L63N_SCP6_0 
I
Register Address :LA[8]
P119
IO_L63P_SCP7_0 
I
Register Address :LA[9]
P120
IO_L62N_VREF_0 
I
Register Address :LA[10]
P121
IO_L62P_0 
I
Register Address :LA[11]
P122
VCCO_0 
+3.3 Volt Power Supply
P123
IO_L37N_GCLK12_0 
I
Register Address :LA[12]
P124
IO_L37P_GCLK13_0 
I
serial i/f pin : RXD2
P125
VCCO_0 
+3.3 Volt Power Supply
P126
IO_L36N_GCLK14_0 I
System 
Clock Input :CLK_16M(16.384MHz)
P127
IO_L36P_GCLK15_0 I
unused 
input (internal pull down)
P128
VCCINT 
+1.2 Volt Power Supply
P129
VCCAUX 
+3.3 Volt Power Supply
P130
GND Ground
P131
IO_L35N_GCLK16_0 I
Input 
for 
evaluation.(internal pullup)
P132
IO_L35P_GCLK17_0 
I
Downstream highway data (from STACK-M) : SHWD[0]
P133
IO_L34N_GCLK18_0 
I
Downstream highway data (from STACK-M) : SHWD[1]
P134
IO_L34P_GCLK19_0 
I
Downstream highway data (from STACK-M) : SHWD[2]
P135
VCCO_0 
+3.3 Volt Power Supply
P136
GND Ground
P137
IO_L4N_0 
O
serial i/f pin to CPUÅFCPU_RXD2
P138
IO_L4P_0 
O
CPU_RXD2 Output control Enable : NRXD2EN
P139
IO_L3N_0 
I
unused input (internal pull down)
P140
IO_L3P_0 
O
Upstream highway data(to STACK-M) : SHWU[2]
P141
IO_L2N_0 
O
Upstream highway data(to STACK-M) : SHWU[1]
P142
IO_L2P_0 
O
Upstream highway data(to STACK-M) : SHWU[0]
P143
IO_L1N_VREF_0 
I
unused input (internal pull down)
P144
IO_L1P_HSWAPEN_0 
I
FPGA functional pin connected Low : HSWAPEN
Pin No.
Pin Name
I/O
Discription Pin Usage
48
KX-NS0131X
12.2. Cabinet and Electrical Parts
Page of 55
Display

Click on the first or last page to see other KX-NS0131X service manuals if exist.

RANDOM: