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7

Shows the external interrupt image.

External interrupt image

• nHALT signal polls using I/O port to achieve the consistency with the existing PBX.

However, in case the CPU(IC1) moves to the sleep mode while the system is halted, the unit returns from the sleep mode receiv-
ing the interrupt signal in CPU(IC1) when nHALT is released in accordance with its specification. 

• The nIRQ[0] interrupt of ASIC(IC2) should be set to the output, which is used as an interrupt output to the CPU (IC1); mainly

DPRAM communication interrupt. 
The LOS signal of PRI-IC(IC301) is the level output which goes to "H" when the line reference is lost.
Consequently, inputting the inverted LOS signal to the CPU (IC1) enables to generate a negative edge interrupt while the line ref-
erence is lost.
Also setting nIRQ4 terminal of CPU(IC1) to I/O port makes polling possible.
The unit is provided with interrupt processing in order to achieve the consistency with the existing PBX.
Polling with I/O port is disable because nRxMF signal of PRI-IC(IC301) is generated in a periodical frame timing.

• The unit should be kept open with a jumper unpopulated to avoid conflicting between output of nIRQ[0] of ASIC(IC2) and the sig-

nal.

8

The reference point of the line interface on the PRI30 card is Point S/T (Point U is not supported.) and the external and internal
line modes are supported as operating mode.
Also, the PRI23/PRI30 cards employ the PRI-IC (IC301) as the IC for Interface. See the "Line Interface Block" or the outline of
the interface connection. Shows the characteristics of the PRI-IC.
See the PRI-IC data sheet for detailed specifications.

Characteristics of the PRI-IC

This card has a relay for loopback test on the primary side of the line to cut and divide into the line failure or the PBX's own fail-
ure, when there is a defect in operation.
Shows The outline diagram of the line interface loopback.

Outline diagram of the line interface

Item

Contents

Remarks

Line Extraction Clock

2.048MHz/PRI30

 

DPLL

Low Jitter DPLL for clk generation (IC302)

 

Elastic Buffer

Two-frame elastic buffer (Rx & Tx)

 

Signaling Controller

• HDLC Controller 
• CAS Controller
• Multiframe synchronization and synthesis ITU-T G.732 etc.

 

FIFO

64Byte x 2     128Byte x 3

 

PCM Highway Interface

2.048Mbps highway Interface

 

µP-Interface

8bit parallel Bus (Intel/Motorola)

Used Intel Mode for PRI30 Card.

9

This card has the local highway at 2.048Mbps rate and local TSW in order to switch the talk channel (Bch), which is extracted
from ISDN primary rate by PRI-IC (IC301), to H.100 interface. (ASIC (IC2) internal module)
Also, the highway assignment is different for that the number of Bch differs in 2.048M system and 1.544M system. Shows the
highway timing.
For more information, see the ASIC (IC2) specification and PRI-IC (IC301) databook.

Highway timing

10

This card transmits and receives data between itself and MPR (EC bus) in a dual port RAM communication basically.
Shows the diagrammic illustration.

DPRAM Communication diagrammic illustration