Panasonic KX-NCP1190XJ (serv.man3) Service Manual ▷ View online
5
KX-NCP1190XJ
3 Specifications
6
KX-NCP1190XJ
4 Technical Descriptions
4.1.
Block Diagram
KX-NCP1190XJ OPB3 BLOCK DIAGRAM
P
C
I_C
LK
P
C
I_R
ST
#
PC
I_
A
D
[31
:0
]
P
C
I_C
/B
E
#
[3
:0
]
P
C
I_P
A
R
P
C
I_F
R
A
M
E
#
P
C
I_IR
D
Y
#
P
C
I_T
R
D
Y
#
P
C
I_ST
O
P
#
P
C
I_ID
SE
L
P
C
I_D
E
V
SE
L
P
C
I_
REQ
P
C
I_C
N
T
#
P
C
I_
P
ERR#
P
C
I_SE
R
R
#
P
C
I_IN
T
A
#
P
C
I_IN
T
B
#
P
C
I_IN
T
C
#
P
C
I_IN
T
D
#
CT
_
C
B
_
A
CT
_
C
B
_
B
/C
T
_F
R
A
M
E
_A
/C
T
_F
R
A
M
E
_B
CT
_
D
[7
:0
]
CT
_
N
E
T
R
E
F
CT
_
M
C
/F
R
_
C
O
M
P
SCLK
SCLK*
2
#
C2
/C
4
/C
16+
/C
1
6
-
nH
A
L
T
P4
[5
:4
]
VR
E
F
+
VR
E
F
-
nB
R
E
Q
nB
A
C
K
nI
R
Q
L_n
R
S
T
nWA
IT
nWR
nR
D
nC
S
I
L
A[11:0]
LD
[7
:0
]
M0DE
[5
:0
]
n
R
ES
ET
PL
L
FH
HW
C
L
K
(4
M
)
DH
W
UHW
C
P
[7:
0]
JUM
P
E
R
R
E
S
E
T-IC
XT
A
L
16.
38
4MH
z
nC
S
2
nC
S
1
nH
A
L
T
nC
S
0
nB
R
E
Q
nB
A
C
K
nI
R
Q
2
nI
R
Q
1
nI
R
Q
0
n
R
ES
ET
nWA
IT
nWR nR
D
nC
S
[5:
0]
A
[22:
0]
D[
1
5
:0
]
nB
U
S
Y
n
R
E
S
E
T
nWR
nR
D
nC
S
A
[19:
0
]
D
[15:
0]
Fl
a
s
h
ROM
4M
SR
A
M
1M
nWR
nR
D
nC
S
A
[16:
0]
D
[7:
0]
XT
A
L
12.
28
8MH
z
BO
AR
D
ID
4
LD
[7
:0
]
L
A
[11:
0
]
nR
D
,n
W
R
n
R
ES
ET
IC2
n
R
ES
ET
n
R
ES
ET
Po
w
e
r
Block
+5
V
+3.
3V
CHP[
7
:0]
CHP[
1
5:8]
CHP[
2
3:16]
C
P
[7:
0]
SAMSON
IC1
H100 native
MVP
compatl
+15V
+40V
+15V
2
IC16
IC500
IC501
DECODER
IC13, IC14, IC15
Option 1
Option 2
Option 3
7
KX-NCP1190XJ
4.2.
Circuit Operation
4.2.1.
Function
• OPB3 CARD is an optional base card.
• MSG4/DPH4/EIO4/ECHO16/ESVM2/ESVM4 card can be mounted.
• 3 optional cards mountable (max).
• Software downloadable from the PBX main unit.
• MSG4/DPH4/EIO4/ECHO16/ESVM2/ESVM4 card can be mounted.
• 3 optional cards mountable (max).
• Software downloadable from the PBX main unit.
4.2.2.
Explanation of the Circuit Operation
OPB3 CARD consists of the following
• CPU Circuit
• Timing Signal Generator Circuit
• Timing Signal Generator Circuit
4.2.3.
CPU Circuit
Composition:
SH1 8bit CPU (IC2)
ROM 512kB (IC500)
RAM 1kB (internal)
128kB (external) (IC501, IC504, IC507)
ROM 512kB (IC500)
RAM 1kB (internal)
128kB (external) (IC501, IC504, IC507)
4.2.4.
Timing Signal Generation Circuit
Composition:
IC1, IC13, IC14, IC15
Circuit Operation:
This is a circuit which generates the timing signals for using for DPH4, MSG4, ESVM2, ESVM4.
These signals are generated from the signals (SHW_FH, SHW_CLK) which are presented from IC1.
These signals are generated from the signals (SHW_FH, SHW_CLK) which are presented from IC1.
8
KX-NCP1190XJ
5 Location of Controls and Components
5.1.
Names and Locations
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