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6

10MHz

RTS CTS

TX+

TX-

EC_bus

H100 bus

28

11

+3.3v

+1.8v +3.3v

+5v

RX+

RX-

RJ45

D15-0

A19-0

12.288MHz

Status

Indication x 4

nRD

nWR

nLBS

nCS1

nCS6

nCS2

nCS3

Local

Reset

nHALT

n

CS1

+3.3V

nRST

ASIC IC2

EC_CLK

EC_AD[15:0]

EC_BE[1:0]

EC_FRAME

EC_TRDY

EC_STOP

EC_INT

EC_PAR

EC_PERR

EC_nRST

EC_IDSEL

EC_DET

LDHW[1:0]

LUHW[1:0]

CT_NETREF

nCT_FRAME_A

CT_CLK_A

CT_D[7:0]

LA[12:0]

LD[7:0]

nRD,nWR

 nCSI

HW_FH

HW_CLK0

HW_CLK1

L_NETREF

nLRST

P0[7:0]

Jumper

+3.3v

DC/DC

Converter

+15v

nBREQ

nBACK

P1[4:0]

P2[0]

5v

Level

Shifter

nWAIT

OSC

16.384MHz

A12-0

D7-0

RXD

TXD

nRD,nWR

nIRQ2

RYnBY

RYnBY

PB[3]

PA[11]

PB[10]

nIRQ[0]

nCS[0]

nCS[0]_S

+3.3V

+3.3V

Flash

8Mbit

(IC5)

(512k x 16)

SRAM

4Mbit

Serge

EMC

Line Interface Block(E1)

Transformer

Serge

EMC

Transformer

CLKOUT(4.096MHz)

Termination

Termination

20MHz

DSP i/f

 DTMF Rcv 24ch

+5V

nINT_ISDN

A4-0 nRD,nWR

D7-0

E1-IC

(IC302)

E1.5o/C1.5o

nC4b

DSTo

DSTi

nFOb

nRES

nIRQ

D[7:0]

A[4:0]

UHW0

BS/nLS

S/nFR/C.1.5i

D7-0

RS232C

+5V

+3.3V

UHW0

DHW0

nCS_ISDN

A2-1

nRD,nWR

D7-0

DSP_nRST

nINT_DSP

DSP_nRST

P2[1]

DHW0(2.048Mbps)

UHW0(2.048Mbps)

+1.8V

nIRQ[1]

nINT_DSP

nINT_DSP

nIRQ3

LOS

nRxMF

nTxMF

LOS

nRxMF nTxMF

P2[

6]

nTxMF

LOS

nRxMF

DSP

(IC303)

A0

A3

DVdd

CVdd

HRDY

HRDY

nRESET

PLLCLK

nCS_DMA

nCS_DMA

P2[7]

CT_LOS

CPU

(IC1)

f=12.288MHz

nBREQ

nWAIT

nRES

nIRQ1

nBACK

nRxMF

LOS

PB[0]

nIRQ0

nIRQ4

nIRQ5

P2[4]

ALM(Red)

P2[3]

LED

(Gr)

HW_CLK0

HW_CLK1(2M)

nHW_FH

nSHW_FH(8kHz)

SHW_FH

nSHW_FH(8kHz)

BDR0

HCNT[1:0]

HBIL

HR/nW

nHDS1,nHDS2

HRDY

nHCS

nHINT

(Red)

P2[2]

DPLL

(MT8941)

nC4b

CVb

MS3-0

16.384MHz

ISDN

_RST

ISDN

_RST

nINT_ISDN

nINT_ISDN

+5V

nRESET

BDX0

BDR1

BFSR(X)0/1

BCLKR(X)0/1

P2[5]

MASK

P3[0]

LOOPB

LOOPB

LoopBack

Test

nCS0

A1

0

Decoder

nCS[0]_S

nCS_DSP

nCS_DSP

nCS_ISDN

nRESET

nRESET

P3[4]

HW_CLK0(4.096MHz)

nHW_FH(8KHz)

HW_CLK1(2.048MHz)

CLKOUT(4.096MHz)

Switch

Line        Extn

TX+

TX-

RX+

RX-

Coaxial

i/f

nWR,nRD

nCS0

D15-09

A1-1

D15-0

A18-1

nCS2

nWR,nRD,nLBS,A0

KX-NCP1188XJ  E1 CARD BLOCK DIAGRAM

(IC3)

3.3v

(256k x 16)

7

The CPU (IC1) is a single chip microcomputer of RISC architecture.
This item describes a memory interface (program & work) and peripheral functions.

Part Name

Size

Purpose

Remarks

Flash
(IC5)

4Mbit
(256K x 16)

Program Area

Flash memory is employed for the software downloading by on-board.

SRAM
(IC3)

4Mbit
(256K x 16)

Work Area

 

Terminals

Function used 

Wait Function 

(Numeral is no. of 

clocks.) 

Remarks 

CS Terminals

Individual Output 

(1)

Individual Output 

(2)

nCS0 (area 0)

-

-

nCS0

1+Programable 

or

1+Programable+WAIT
Terminals

Used for Flash memory CS.

nCS1 (area 1)

nCASH (DRAM)

-

nCS1

Read  1/Write  2  or
2+WAIT Terminals

Used for ASIC (IC2) (ASIC) CS

nCS2 (area 2)

-

-

nCS2

1+Programable 

or

1+Programable+WAIT
Terminals

Used for SRAM (Basic) CS. Work
Area

nCS3 (area 3)

nCASL (DRAM)

-

nCS3

Read  1/Write  2  or
2+WAIT Terminals

CS Reserve

nCS4 (area 4)

PA0 (I/O)

TIOCA0 (Timer)

nCS4

Read  1/Write  2  or
2+WAIT Terminals

CS Reserve

nCS5 (area 5)

PA1 (I/O)

nRAS (DRAM)

nCS5

Read  1/Write  2  or
2+WAIT Terminals

CS Reserve

nCS6 (area 6)

PA2 (I/O)

TIOCB0 (Timer)

nCS6

1+Programable 

or

1+Programable+WAIT
Terminals

Used for peripheral LSI CS.
Used for framer IC, DSP CS.

nCS7 (area 7)

PA3 (I/O)

nWAIT

nWAIT

Read  1/Write  2  or
2+WAIT Terminals

Used for Input Wait Terminals.

Chip Select

Address

Device Bit Wide

Assignment 

Device

Bus Cycle

Remarks

nCS0

0000000h
l
0FFFFFFh

16bit

4M_Flash
(IC 5)

2 Clock (1+Long Wait1)

Port allocation of word by static bus sizing
Bus cycle has same setting as Area 2
(nCS2).

nCS1

1000000h
l
1FFFFFFh

8bit

ASIC (IC2)

2+WAIT Terminals

Port allocation of byte by static bus sizing. 

nCS2

A000000h
l
AFFFFFFh

16bit

4M_SRAM
(IC 3)

2 Clock (1+Long Wait1)

Port allocation of word by static bus sizing
Bus cycle has same setting as Area 0
(nCS0).

nCS6

6000000h
l
6FFFFFFh

8bit

E1_IC
(IC302)

3 Clock (1+Long Wait2)

Port allocation of byte by static bus sizing.

8

• nHALT signal is consistent with the existing PBX and performs polling by I/O port.

However, when the CPU (IC1) goes to Sleep Mode at HALT, the CPU (IC1) is enabled for interruption on release nHALT and
return from Sleep Mode.

• The nIRQ[0] interrupt of ASIC (IC2) is set to output and the interrupt output is to the CPU (IC1) (Mainly, DPRAM communication

interrupts).

• The LOS signal of the T1-IC (IC302) is a level output which goes "H level" at the line reference lost. Thus, 

↓ edge interruption is

available at the line reference lost by inputting the inversion signal of the LOS to the CPU (IC1). The polling operation is also pos-
sible by setting the nIRQ4 terminal of the CPU (IC1) to i/o port. 
(The configuration with the interruption processing is to give a consistency with the existing PBX.)

• Since the nRxMF signal of the T1-IC (IC302) occurs in periodic frame timing, the polling by i/o port is impossible.

9

E1 card uses the E1-IC (IC302)(Mitel) as the IC for the line interface.
Also, see the E1-IC (IC302) Data Sheet for the detailed specifications.

This card has a relay for loopback test on the primary side of the line to cut and divide into the line failure or the PBX's own fail-
ure, when there is a defect in operation.

Item

Contents

Remarks

Line Extraction Clock

2.048MHz

 

DPLL

Low Jitter DPLL for calk generation

 

Elastic Buffer

Two-frame elastic buffer (Rx & Tx)

 

Signaling Controller

• HDLC0: Data link (4, 8, 12, 16, 20kbps) 
• HDLC1: CCS times slot 16

Built-in two pieces

FIFO (HDLC0)

128Byte x 2

TX/RX Variable in the range from 16 Byte to 128Byte in
increments of 16Byte.

FIFO (HDLC1)

128Byte x 2

TX/RX Variable in the range from 16 Byte to 128Byte in
increments of 16Byte.

PCM Highway Interface

ST-BUS Interface (2.048Mbps)

 

µP-Interface

8bit parallel Bus (Intel/Motorola)

Used Intel Mode for E1 Card.