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37

1. DC voltage measurements are taken with an oscilloscope or a tester with a ground.
2. The schematic diagrams and circuit board may be modified at any time with the development of new technology.

38

Port

Pin

Terminals

I/O

ACT

Terminals Contents

PA
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

15

68

nIRQ3

I

L

Reserve (interrupt)

14

67

nIRQ2

I

L

E1_IC (IC302) interrupt

13

66

nIRQ1

I

L

Interrupt for SAMSON (ASIC) (mainly DPRAM communication
interrupt for MPR)

12

65

nIRQ0

I

L

DC power down recovery detection inversion signal of CPU (IC1)
inversion signal (L:recovery)

11

64

PA11

O

L

UART port for request to send [RTS0] (RS232C)

10

62

PA10

I

L

UART port for clear to send [CTS0] (RS232C)

9

61

PA9

-

-

Reserve (general-purpose i/o)

8

60

nBREQ

I

L

Bus request signal (bus arbitration)

7

58

nBACK

O

L

Bus acknowledge signal (bus arbitration)

6

57

nRD

O

L

Read signal(bus control)

5

56

nLBS

O

L

Low byte strobe signal(bus control)

4

55

nWR

O

L

Write signal(bus control)

3

54

nWAIT

O

L

Wait signal(bus control)

2

53

nCS6

O

L

Chip select 6 signal(bus control)

1

52

PA1

-

-

Reserve (Chip Select 5 signal)

0

51

PA0

-

-

Reserve(Chip Select 4 signal)

39

PB
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

15

100

nIRQ7

-

-

Reserve(interrupt)

14

99

nIRQ6

-

-

Reserve(interrupt)

13

98

nIRQ5

I

L

Line Reception Multi-frame Boundary Signal Input (nRxMF)

12

97

nIRQ4

I

L

Line Reference Lost Interruption, or Polling by i/o Setting (LOS)

11

96

PB11

-

-

Reserve(general-purpose i/o)

10

95

PB10

-

-

Reserve(general-purpose i/o)

9

94

TxD0

O

H/L

UART port to send data [TxD0] (RS232C)

8

93

RxD0

I

H/L

UART port to receive data [RxD0] (RS232C)

7

91

PB7

-

-

Reserve(general-purpose i/o)

6

90

PB6

-

-

Reserve(general-purpose i/o)

5

89

PB5

I

L

For manufacturing test L:Manufacturing test mode

4

87

PB4

I

L

For card single debugging L:debug mode

3

86

PB3

I

L

Flash memory busy input (L:busy)

2

85

PB2

I

L

Reserve(general-purpose i/o)

1

84

PB1

I

L

Reserve(general-purpose i/o)

0

83

PB0

I

H

CPU (IC1) inversion signal (H:inversion)

Port

Pin

Terminals

I/O

ACT

Terminals Contents

40

Port

Pin

Terminals

I/O

ACT

Terminals Contents

P0
 
 
 
 
 
 
 

7

149

PO[7]

I

H/L

Reserve (Jumper setup)

6

148

PO[6]

I

H/L

Reserve (Jumper setup)

5

147

PO[5]

I

H/L

Reserve (Jumper setup)

4

146

PO[4]

I

H/L

Hardware version control bit2 (Jumper setup)

3

145

PO[3]

I

H/L

Hardware version control bit1 (Jumper setup)

2

144

PO[2]

I

H/L

Hardware version control bit0 (Jumper setup)

1

143

PO[1]

I

H/L

Number of lines info bit1 (Jumper setup)

0

142

PO[0]

I

H/L

Number of lines info bit0 (Jumper setup)

P1
 
 
 
 
 
 
 

7

158

P1[7]

-

-

Reserve

6

157

P1[6]

-

-

Reserve

5

156

P1[5]

-

-

Reserve

4

155

P1[4]

-

-

Line Condition Display LED...Green Data Link (L:Blink)

3

154

P1[3]

O

L

Line Condition Display LED...Green Sync (L:Blink)

2

153

P1[2]

O

L

Line Condition Display LED...Red AIS (L:Blink)

1

152

P1[1]

O

L

Line Condition Display LED...Red RAI (L:Blink)

0

151

P1[0]

O

L

Line Condition Display LED...Red Sync Err (L:Blink)

P2
 
 
 
 
 
 
 

7

168

P2[7]

O

H

Line Reference Lost Signal Output (H:Reference Lost)

6

167

P2[6]

O

L

Line Transmission Multi-frame Boundary Signal Output
(nTxMF)

5

166

P2[5]

O

H

"Line Reference Lost Interruption Mask Output (O: Mask Can-
cellation 1: Mask)"

4

165

P2[4]

I

H

Reserve

3

164

P2[3]

O

L

Card Operating State Display LED...Green(L:Blink)

2

163

P2[2]

O

L

Card Operating State Display LED...Red (L:Blink)

1

162

P2[1]

O

L

Reserve

0

161

P2[0]

O

L

E1-IC(IC302) Reset (H:Reset)