DOWNLOAD Panasonic UF-490 / UF-4000 / UF-4100 / UF-490YC / UF-490YR Service Manual ↓ Size: 1.6 MB | Pages: 118 in PDF or view online for FREE

5

P

aper

F

eed

Solenoid

A-point

Sensor

B-point

Sensor

Speak

er

TEL

LINE

Co

v

er Sensor

50MHz

CIS

IA2008-MA30C (A4)

or

IH2010-MB51B (B4)

Work Memory

Page Memory

SDRAM

8MB

Scanner

/ Pr

inter

Motor

F

ax Bloc

k Diag

ra

m

PNL PCB

Key 

Matrix

and LED

MN860741

16MHz

Motor

Driver

7.235MHz

10.923MHz

LSU UNIT

Pa

rallel  I/F

SHINE

(DZAC000273)

for 16pels/mm

Pr

inting

for 600dpi

Pr

inting

5MHz

Stamp

Fa

n

ILS PCB

Program

FROM

2MB

24.576MHz

MN195006

Si3021

Si3015

Handset

(option)

SC PCB

IEEE 1284

Transceiver

CPU

(V850/MA1)

LCD Unit

CPU

P

o

w

er Inlet

A

CI PCB

Heater

Control

+5VP

+5V

+24V

-12V

+3.3V

Low Voltage 

Power Supply

AC

Ther

mistor

Fuser LAMP

Ther

mostat

Specific Countr

ies Only

.

Not  Mounted

for USA, Canada

Registr

ation

Sensor

Exit

Sensor

B4 Width

Sensor

High Voltage

Power Supply

P

aper Chec

k

Sensor

T

oner

Sensor

SNSE PCB

ETXDN342A2E (120V)

ETXDN342E2E (230V)

SNST PCB 2/2

SNST PCB 1/2

6

The System Control Block consists of the following IC that control the general Fax functions.

CPU

V850E/MA1

(IC1)

SHINE

DZA

C000273

(IC3)

S-DRAM 8MB

(IC6)

FR

OM 2MB

(IC5)

      

MN860741

(IC18)

MODEM

MN195006

(IC9)

DA

A

 Si3021,

Si3015

(IC11, 12)

A-BUS 3.3V

D-BUS 3.3V

PNL CPU

LSU

CIS

IEEE 1284

T

ransceiv

er

(IC28)

LINE

PC

 IEEE 1284 I/F

7

1. System CPU

The System CPU (V850E/MA1) is a 32-bit RISC (Reduced Instruction Set Computer) type of CPU and 
DMA Control, Serial Communication Port, Timer Control, Interrupt Control, DRAM Control, and I/O Port 
are integrated into Single (1) Chip. Mask ROM (128k byte) is already installed and it controls the Real 
Time OS, High Speed managing Task and Boot Programming.

• DMA Control

It has a 4ch DMA Control and is used to transfer data between the following devices.
Image Data Memory (DRAM) 

←→ Image Data Memory (DRAM)

• Serial Communication Port

It has a 2ch Serial Communication Port and is used to interface the following devices.
CPU 

←→ Panel Unit (Panel CPU)

• Timer Control

It is used to program the standard timer, the creation of the charge AC frequency.

• Interrupt Control

It controls receipt & transfer to CPU the interrupt from SHINE, Modem.

• S-DRAM Control

It generates S-DRAM Control Signal and Refresh Control when the power is ON.

• I/O Port

It is used to control lines, reset control around LSI, and so on.

2. Integrated Gate Array (SHINE)

• DZAC000273 (SHINE) is a Highly Integrated Gate Array which provides the function of System 

Control, Scanning Control, Recording Data Control, LP Engine Control, PC Interface.

• 2-1. System Control Block

•DMA Control

It is used to transfer data between the following devices.
Scanning Control LSI (MN860741) 

→ Memory (S-DRAM) : Scanning Route

Memory (S-DRAM) 

→ LP     : Recording Route

PC 

←→ Memory (S-DRAM) : PC I/F Route

Memory (S-DRAM) 

←→ Memory (S-DRAM) : Editing Route

•S-DRAM Control

It generates S-DRAM Control Signal. It shares S-DRAM with the CPU by using the Bus Hold 
Mode function of the CPU.

•System Control Signals Generation

It generates various system control signals for the CPU assistance.

•CIS Control Signal Generation

It generates CIS control signals. 
CIS stands for Contact Image Sensor, which is compact scanning Device.

•Black Shading Correction

To suppress dispersion of CIS pixel elements, it compares with a black signal (LED is off) as a 
base level, it corrects analog data level by controlling values of external resistors.

8

•Scanning LSI Control Signal Generation

It generates control signals for a scanning LSI (MN860741). A reduction of sub scan is 
proceeded with this block.

•Scanning Data Transfer Control Circuit

The Scanning Image data (Binary or Multi-level Gray Scale) form Scanning LSI (MN860741) are 
Serial. This Circuit converts the Serial Image data to the Parallel Image data, and transfers to the 
Memory through DMA controller. It is used for processing the data such as masking the data, 
reversing the data etc.

•Motor control

SMA7027M (IC26), which generates control pulse signals of a motor which is used for scanning 
and recording.

•Reduction / Enlargement Control Circuit

This circuit is used to process the received data to fit on the recording paper, according to the 
Fax Parameter Settings.

•Image Range Isolation Circuit

It identifies the halftone picture range and controls smoothing, Binary Gray Scale Conversion, 
and Laser pulse width control to eliminate blocking of the recording picture which has undergone 
error diffusion or other process.

•Picture Quality Correction Circuit (Smoothing)

When the receiving data (8 dot/mm x 7.7, 15.4 line/mm) is converted to 16 dot/mm x 15.4 line/ 
mm resolution, the current printed data and 15 surrounding printed data are sent to the 
Smoothing ROM through 16 bit line and the ROM sends smoothed dot data. As a result of this 
operation, the distorted curved lines are smoothed.

•Binary Gray Scale Conversion

The signal of a binary-level image such as copying is converted into a multiple-value (64-scale) 
image signal for multiple-value recording. 
A maximum of 5-by-5 pixels around an area is referred to in layers for conversion into 
multiple-value signal.

•Laser Pulse Width Control

After smoothing, the SHINE controls Laser pulse width by the software setting of the print quality.

•Gray-Level Enhancement

This control function allows expressing higher-level scales than using a recorded signal, by 
reducing line density into 1/2 or 1/3 on the original after binary-to-multiple value conversion. This 
capability increases reproduction of gray scale images such as photographs.

•Synchronization Control Circuit

This circuit is used to synchronize the output of the recorded data with the horizontal 
synchronizing output signal from the printer for each line.