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1

GND

Gnd

Ground

2

VDDPLL_1.8

P

1.8V analog VDD

3

VDDA_3.3

P

3.3V analog VDD

4

RX-

I/O

Physical receive or transmit signal (- differential)

5

RX+

I/O

Physical receive or transmit signal (+ differential)

6

TX-

I/O

Physical transmit or receive signal (- differential)

7

TX+

I/O

Physical transmit or receive signal (+ differential)

8

XO

O

Crystal feedback 
This pin is used only in MII mode when a 25 MHz crystal is used. 
This pin is a no connect if oscillator or external clock source is used, or
if RMII mode is selected.

9

XI  / 

REFCLK

I

Crystal / Oscillator / External Clock Input 
MII Mode:

25MHz +/-50ppm (crystal, oscillator, or external clock)

RMII Mode:

50MHz +/-50ppm (oscillator, or external clock only)

10

REXT

I/O

Set physical transmit output current 
Connect a 6.49K

Ω resistor in parallel with a 100pF capacitor to ground

on this pin. See KSZ8041NL reference schematics.

11

MDIO

I/O

Management lnterface (MII) Data I/O 
This pin requires an external 4.7K

Ω pull-up resistor.

12

MDC

I

Management Interface (MII) Clock Input 
This pin is synchronous to the MDIO data interface.

13

RXD3 / 

PHYAD0

Ipu/O

MII Mode: 
Config Mode:

Receive Data Output[3]

(2)

 /

The pull-up/pull-down value is latched as PHYADDR[0]
during power-up / reset. See “Strapping Options” sec-
tion for details."

14

RXD2 / 

PHYAD1

Ipd/O

MII Mode: 
Config Mode: 

Receive Data Output[2]

(2)

 / 

The pull-up/pull-down value is latched as PHYADDR[1]
during power-up / reset. See “Strapping Options” sec-
tion for details."

15

RXD1 / 

RXD[1] / 

PHYAD2

Ipd/O

MII Mode:

Receive Data Output[1]

(2)

 / 

RMII Mode:

Receive Data Output[1]

(3)

 / 

Config Mode:

The pull-up/pull-down value is latched as PHYADDR[2]
during power-up / reset. See “Strapping Options” sec-
tion for details."

16

RXD0 /

RXD[0] / 

DUPLEX

Ipu/O

MII Mode:

 Receive Data Output[0]

(2)

 / 

RMII Mode:

Receive Data Output[0]

(3)

 / 

Config Mode:

Latched as DUPLEX (register 0h, bit 8) during power-
up / reset. See “Strapping Options” section for details."

17

VDDIO_3.3

P

3.3V digital VDD

18

RXDV /

CRSDV / 

CONFIG2

Ipd/O

MII Mode: 

Receive Data Valid Output /

RMII Mode:

Carrier Sense/Receive Data Valid Output /

Config Mode:

The  pull-up/pull-down  value is latched as CONFIG2
during power-up / reset. See “Strapping Options” sec-
tion for details."

19

RXC

O

MII Mode: 

Receive Clock Output

20

RXER / 

RX_ER / 

ISO

Ipd/O

MII Mode: 

Receive Error Output /

RMII Mode:

Receive Error Output /

Config Mode:

The pull-up/pull-down value is latched as ISOLATE dur-
ing power-up / reset. See “Strapping Options” section
for details."

21

INTRP

Opu

Interrupt Output: Programmable Interrupt Output 
Register 1Bh is the Interrupt Control/Status Register for programming
the interrupt conditions and reading the interrupt status. Register 1Fh bit
9 sets the interrupt output to active low (default) or active high.

22

TXC

O

MII Mode: 

Transmit Clock Output

23

TXEN / 
TX_EN

I

MII Mode:

Transmit Enable Input /

RMII Mode: 

Transmit Enable Input

24

TXD0 / 
TXD[0]

I

MII Mode:

Transmit Data Input[0]

(4)

 /

RMII Mode: 

Transmit Data Input[0]

(5)

25

TXD1 / 
TXD[1]

I

MII Mode: 

Transmit Data Input[1]

(4)

 / 

RMII Mode: 

Transmit Data Input[1]

(5)

14

26

TXD2 /

I

MII Mode: 

Transmit Data Input[2]

(4)

 /

27

TXD3 /

I

MII Mode: 

Transmit Data Input[3]

(4)

 /

28

COL / 

CONFIG0

Ipd/O

MII Mode:

Collision Detect Output /

Config Mode:

The  pull-up/pull-down  value is latched as CONFIG0
during power-up / reset. See “Strapping Options” sec-
tion for details."

29

CRS / 

CONFIG1

Ipd/O

MII Mode:
 

Carrier Secse Output /

Config Mode:

The  pull-up/pull-down  value is latched as CONFIG1
during power-up / reset. See “Strapping Options” sec-
tion for details."

30

LED0 / 

NWAYEN

Ipu/O

LED Output: 

Programmable LED0 Output /

Config Mode:

Latched as Auto-Negotiation Enable (register 0h, bit
12) during power-up / reset. See “Strapping Options”
section for details.

The LED0 pin is programmable via register 1Eh bits [15:14], and is 
defined as follows.

LED mode = [10]
Reserved

LED mode = [11]
Reserved

31

LED1 / 

SPEED

Ipu/O

LED Output: 

Programmable LED1 Output /

Config Mode:  Latched as SPEED (register 0h, bit 13) during power-

up / reset. See “Strapping Options” section for details. 

The LED1 pin is programmable via register 1Eh bits [15:14], and is 
defined as follows.

LED mode = [10]
Reserved

LED mode = [11]
Reserved

32

RST#

I

Chip Reset (active low)

PADDLE

GND

Gnd

Ground

15

1. P = Power supply.

Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipd = Input with internal pull-down (40K +/-30%).
Ipu = Input with internal pull-up (40K +/-30%).
Opu = Output with Internal pull-up (40K +/-30%).
Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
lpd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.

2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents valid data to

MAC through the MII. 
RXD[3..0] is invalid when RXDV is de-asserted.

3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS-DV is asserted, two

bits of recovered data are sent from the PHY.

4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid data from

the MAC through the MII. TXD[3..0] has no effect when TXEN is de-asserted.

5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits

of data are received by the PHY from the MAC.

16