Panasonic KX-FP363RU Service Manual ▷ View online
NO.
SIGNAL
I/O
POWER SUPPLIED
VOLTAGE
DESCRIPTION
66
DB3
I/O
3.3V
CPU DATA BUS 3
67
DB2
I/O
3.3V
CPU DATA BUS 2
68
DB4
I/O
3.3V
CPU DATA BUS 4
69
DB1
I/O
3.3V
CPU DATA BUS 1
70
DB5
I/O
3.3V
CPU DATA BUS 5
71
VDD (3.3V)
-----
POWER SOURCE (+3.3V)
72
VSS
GND
POWER SOURCE (GND)
73
VSS
GND
POWER SOURCE (GND)
74
VDD (3.3V)
3.3V
POWER SOURCE (+3.3V)
75
DB0
I/O
3.3V
CPU DATA BUS 0
76
DB6
I/O
3.3V
CPU DATA BUS 6
77
DB7
I/O
3.3V
CPU DATA BUS 7
78
XROMCS
O
3.3V
ROM (IC523) CHIP SELECT
79
RD
O
3.3V
CPU RD
80
WR
O
3.3V
CPU WR
81
ADR0
O
3.3V
CPU ADDRESS BUS 0
82
ADR1
O
3.3V
CPU ADDRESS BUS 1
83
ADR2
O
3.3V
CPU ADDRESS BUS 2
84
ADR3
O
3.3V
CPU ADDRESS BUS 3
85
ADR4
O
3.3V
CPU ADDRESS BUS 4
86
ADR5
O
3.3V
CPU ADDRESS BUS 5
87
VSS
GND
POWER SOURCE (GND)
88
VDD (2.5V)
-----
POWER SOURCE (+2.5V)
89
ADR6
O
3.3V
CPU ADDRESS BUS 6
90
ADR7
O
3.3V
CPU ADDRESS BUS 7
91
ADR8
O
3.3V
CPU ADDRESS BUS 8
92
ADR9
O
3.3V
CPU ADDRESS 9
93
ADR10
O
3.3V
CPU ADDRESS 10
94
ADR11
O
3.3V
CPU ADDRESS 11
95
ADR12
O
3.3V
CPU ADDRESS 12
96
RBA0
O
3.3V
ROM/RAM BANK ADDRESS 0
97
RBA1
O
3.3V
ROM/RAM BANK ADDRESS 1
98
RBA2
O
3.3V
ROM/RAM BANK ADDRESS 2
99
RBA3
O
3.3V
ROM/RAM BANK ADDRESS 3
100
RBA4
O
3.3V
ROM/RAM BANK ADDRESS 4
101
RBA5
O
3.3V
ROM/RAM BANK ADDRESS 5
102
RBA6/IOP96
O
3.3V
A19
103
STB1
O
3.3V
STROBE SIGNAL OUTPUT TO THERMAL HEAD
104
STB2
O
3.3V
STROBE SIGNAL OUTPUT TO THERMAL HEAD
105
STB3
O
3.3V
NOT USED
106
XRESET
I
3.3V
RESET INPUT
107
VDD (3.3V)
-----
POWER SOURCE (+3.3V)
108
VSS
GND
POWER SOURCE (GND)
109
VSS
GND
POWER SOURCE (GND)
110
VDD (3.3V)
-----
POWER SOURCE (+3.3V)
111
XORESET
O
3.3V
RESET OUTPUT
112
VDD(5V)
3.3V
POWER SOURCE (+5V)
113
VSS
GND
POWER SOURCE (ANALOG GND)
114
XRESETI
I
3.3V
RESET INPUT
115
WDERR
O
3.3V
WATCHED ERROR OUTPUT SIGNAL
116
THDAT
O
3.3V
RECORDED IMAGE OUTPUT
117
THCLK
O
3.3V
CLOCK OUTPUT FOR DATA TRANSFER
118
THLAT
O
3.3V
PULSE OUTPUT FOR DATA LATCH
119
STBNP
I
3.3V
INPUT PORT (TEST)
120
RM0/IOP
O
3.3V
RX MOTOR A PHASE
121
RM1/IOP
O
3.3V
RX MOTOR B PHASE
122
RM2/IOP
O
3.3V
RX MOTOR /A PHASE
123
RM3/IOP
O
3.3V
RX MOTOR /B PHASE
124
RXE/IOP
O
3.3V
RX MOTOR ENABLE SIGNAL
125
TMO
O
3.3V
TX MOTOR A PHASE
126
VDD (2.5V)
3.3V
POWER SOURCE (+2.5V)
127
VSS
GND
POWER SOURCE (GND)
128
TM1/IOP
O
3.3V
TX MOTOR B PHASE
129
TM2/IOP
O
3.3V
TX MOTOR /A PHASE
130
TM3/IOP
O
3.3V
TX MOTOR /B PHASE
131
TXE/IOP
O
3.3V
TX MOTOR ENABLE SIGNAL
125
KX-FP363RU
NO.
SIGNAL
I/O
POWER SUPPLIED
VOLTAGE
DESCRIPTION
132
KSTART
O
3.3V
OPERATION PANEL CONTROL
133
KLATCH
O
3.3V
OPERATION PANEL CONTROL
134
KSCLK
O
3.3V
OPERATION PANEL CONTROL
135
KTXD
O
3.3V
OPERATION PANEL CONTROL
136
KRXD
I
3.3V
OPERATION PANEL CONTROL
137
FMEMCLK/IOP
O
3.3V
OUTPUT PORT (THON)
138
FMEMDI/IOP
O
3.3V
OUTPUT PORT (LINERLY)
139
ADSEL1
O
3.3V
CHANNEL SELECT SIGNAL FOR AIN2
140
VDDA (2.5V)
3.3V
POWER SOURCE (ANALOG +2.5V)
141
VREFB
A
2.5V
A/D CONVERTER´S ZERO STANDARD VOLTAGE
OUTPUT
OUTPUT
142
VCL
A
3.3V
ANALOG PART STANDARD VOLTAGE SIGNAL
143
VREFT
A
3.3V
A/D
CONVERTER´S
FULL
SCALE
VOLTAGE
OUTPUT
144
VSSA
GND
POWER SOURCE (ANALOG GND)
126
KX-FP363RU
7.3.4. FLASH MEMORY (IC523)
The 512KB ROM (FLASH MEMORY) carries a common area of 32KB and bank areas which each have 8KB (BK4~BK63). The
addresses from 0000H to 7FFFH are for the common area and from 8000H to 9FFFH are for the bank areas.
addresses from 0000H to 7FFFH are for the common area and from 8000H to 9FFFH are for the bank areas.
7.3.5. DYNAMIC RAM (IC503)
The DRAM serves as CPU and receives memory.
The address is F200H~F3FFH (DRAM access window 1) and F600H~F7FFH (DRAM access window 2).
7.3.6. RESET CIRCUIT (WATCH DOG TIMER)
The output signal (reset) from pin 4 of the voltage detect IC (IC507) is input to the ASIC (IC501) 114 and 106 pins.
1. During a momentary power interruption, a positive reset pulse of 50~70 msec is generated and the system is reset completely.
2. The watch dog timer, built-in the ASIC (IC501), is initialized by the CPU about every 1.5 ms.
When a watch dog error occurs, pin 115 of the ASIC (IC501) becomes low level.
The terminal of the ´WDERR´ signal is connected to the reset line, so the ´WDERR´ signal works as the reset signal.
127
KX-FP363RU
7.3.7. RTC BACKUP CIRCUIT
1. Function
This unit has a lithium battery (BAT501) which works for Real Time Clock IC (RTC: inside IC501).
The RTC continues to work, backed up by a lithium battery even when the power switch is OFF.
The user parameters for autodial numbers, the system setup data and others are in the FLASH ROM (IC523).
2. RTC Inside (IC501) Backup Circuit Operation
When the power switch is turned ON, power is supplied through Q506 to the RTC (inside IC501). At this time, the voltage at
pin 14 of the IC501 is +2.5V. When the power switch is turned OFF, the BAT501 supplies power to RTC through D503 and
Q506. The voltage at pin 14 of IC501 is about +2.2V. When the power switch is OFF and the voltage of +3.3V decreases, pin
14 of RTC (IC501) becomes roughly the same voltage as the battery voltage. RTC goes into the backup mode, in which the
power consumption is lower.
pin 14 of the IC501 is +2.5V. When the power switch is turned OFF, the BAT501 supplies power to RTC through D503 and
Q506. The voltage at pin 14 of IC501 is about +2.2V. When the power switch is OFF and the voltage of +3.3V decreases, pin
14 of RTC (IC501) becomes roughly the same voltage as the battery voltage. RTC goes into the backup mode, in which the
power consumption is lower.
128
KX-FP363RU
