Panasonic KX-FM131BX / KX-FM131CX Service Manual ▷ View online
2.3.3.4.1. Digital Block Diagram
IC501
ASIC
ADR[15:13]
RBA[6:0]
ADR[12:0]
DB[7:0]
XRD
XWR
XR
OMCS
XRAMCS
XMDMCS
IC502
RO
M
IC504
SRAM
IC505
MODEM
A[17:0]
D[7:0]
XRD
XCS
A[16:0]
D[7:0]
XRD
XWR
XCS
A[4:0]
D[7:0]
XRD
XWR
XCS
XWDERR
IN
OUT
GND
+5V
+3.3V
TO
OP-P
ANEL
KST
AR
T
,KLA
TCH
KSCLK,KTXD
KRXD
,JOG1,JOG2
TO
CIS
F1,FTG
CISLEDON
VIDEO
TO
THRMAL
HEAD
THD
A
T
,THCLK,THLA
T
STB1,STB2,STB3
TM
+24V
TO
M
OTO
R
TM[3:0],TXE
TO
PO
WER
SUPPL
Y
+24V
,+5V
,PG,DG
OP-RESET
+24V
PDET
XRESETI
XORESET
XRESET
XBA
CKEN
RESET
-
IC
+3V/BA
TT
+5V/BA
TT
VCC
BA
TT
+
-
24MHz
32.768KHz
TX
RX
TO
ANALOG
PCB
SP-AMP
TO
SPEAKER
A[12:0]
RBA[5:0]
A[11:0]
RBA[2:0]
A[4:0]
+5V
XRAS
XCAS
A[9:0]
D[7:0]
XRD
XWR
XRAS
XCAS
IC503
DRAM
A[7:4]
RBA[5:0]
FILMEND
P
APER
TO
P
SENSOR
LED ON
PS501
IC510
FLASH
XRD
XWR
CLE
ALE
W/P
R/B
XCS
D[7:0]
32.256MHz
FMEMDI
FMEMDO
FMEMCS
FMEMCLK
TO
POSITIO
N
SW
+5V
CN505
CN504
CN508
CN507
CN506
CN509
PS501
CN503
TO
MIC
CN512
BA
G
DIR
IC550
CN501,502
MID
A
TA
MICLK
MILA
T
IC551
ANALOG ASIC
TO
RF UNIT
CN511
S-ENB
,CRESET
,CSO
,CB
USY2
CSI,CB
USY1,CCLK
65
KX-FM131BX / KX-FM131CX
You also need to check the signal lines listed here [List 1] when the unit fails to boot up the system. Those signal lines should
remain normal. Other signal lines are not directly related to that failure even if they have faults or troubles.
remain normal. Other signal lines are not directly related to that failure even if they have faults or troubles.
As long as these signals remain normal, once the power is turned on, each IC can repeatedly output 5V (H) and 0V (L). The
following shows NG and normal wave patterns.
following shows NG and normal wave patterns.
NG Wave pattern (Refer to NG EXAMPLE)
66
KX-FM131BX / KX-FM131CX
Normal Wave Patterns
Remarks:
When you use an oscilloscope to judge whether a signal to be tested is normal or NG, perform the signal check in exactly the
same order as in [List 1]. (If the ASIC fails to access the ROM, the ASIC cannot access SRAM or DRAM normally.)
same order as in [List 1]. (If the ASIC fails to access the ROM, the ASIC cannot access SRAM or DRAM normally.)
The digital circuit actually operates according to the timing combinations of these signals. If the timing of these signals is even
slightly delayed, the circuit will not work. Nor will it if the IC is defective and the output voltage level is not normal although the timing
of these signals is accurate enough to meet the specifications. (Make sure that your oscilloscope is calibrated before starting a
test.)
slightly delayed, the circuit will not work. Nor will it if the IC is defective and the output voltage level is not normal although the timing
of these signals is accurate enough to meet the specifications. (Make sure that your oscilloscope is calibrated before starting a
test.)
Therefore, it is imperative to confirm whether each IC outputs the signal at the correct level. (See the I/O Pin No. Diagram.) The
signal level should be constantly output at between 5V (H) and 0V (L) as described earlier.
signal level should be constantly output at between 5V (H) and 0V (L) as described earlier.
Note:
Simply check the output level and make sure if the IC repeatedly outputs the signal at between 5V (H) and 0V (L).
67
KX-FM131BX / KX-FM131CX
I/O and Pin No. Diagram
68
KX-FM131BX / KX-FM131CX
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