Panasonic KX-FB423RU-W Service Manual ▷ View online
8.3. FACSIMILE SECTION
8.3.1. DIGITAL SECTION
8.3.1.1. DIGITAL BLOCK DIAGRAM
IC501
ASIC
ADR[15:13]
RBA[5:0]
ADR[12:0]
DB[7:0]
XRD
XWR
XR
OMCS
XOPRBE
XMDMCS
IC523
FLASH
IC520
D[7:0]
T
o
Ther
mal
Head
DRB[7:0]
XCAS2
GA
TE ARRA
Y
IC505
MODEM
A[17:0]
D[7:0]
XRD
XCS
A[4:0]
D[7:0]
XRD
XWR
XCS
XWDERR
IN
OUT
GND
TO
OP-P
ANEL
KST
AR
T
,KLA
TCH
KSCLK,KTXD
KRXD
TO
CIS
VIDEO
TO
THRMAL
HEAD
THD
A
T
,THCLK,
THLA
T
STB1,STB2
TM
+24V
PRINTING
TO
(MO
T
OR)
RM[3:0],RXE
TO
PO
WER
SUPPL
Y
+24V
,+5V
,PG,DG
OP-RESET
+24V
XRESETI
XORESET
XRESET
XBA
CKEN
RESET
-IC
+3.3V/BA
TT
+2.5V/BA
TT
BA
TT
+
-
24MHz
32.768KHz
TX
RX
TO
ANALOG
PCB
A[12:0]
RBA[5:0]
A[4:0]
+5V
XRAS
XCAS
A[9:0]
D[7:0]
XRD
XWR
XRAS
XCAS
IC503
IC507
DRAM
A[7:4]
RBA[5:0]
PT
OP
CO
VER
SENSOR/
LED ON
PS1
+3.3V
CN504
CN503
CN505
CN516
SPEAKER
CN510
CIS
TO
TO
CARRIA
GE
(MO
T
OR)
TM[3:0]
CN515
ADF
TO
ADF SENSOR
AND
(MO
T
OR)
VIA
ANALOG
BO
ARD
TM[3:0]
CN513
CN506
CN511
SW1
REED SW
CN514
SENSER LED ON2
(FILM DETECTION)
CIS POSITION
SENSER
IC525
MO
T
OR DR
V
CISLEDON
XCAS2
32.256MHz
+3.3V
VDET
Q505
+3.3V
+2.5V
Q506
+2.5V/BA
TT
+3.3V/BA
TT
KX-FB423RU-W : DIGITAL BLOCK DIAGRAM
SPEAKER
AMP
125
KX-FB423RU-W
This custom IC is used for the general FAX operations.
1. CPU:
This model uses a Z80 equivalent to the CPU operating at
12 MHz. Most of the peripheral functions are performed by
custom-designed LSIs. Therefore, the CPU only works for
processing the results.
12 MHz. Most of the peripheral functions are performed by
custom-designed LSIs. Therefore, the CPU only works for
processing the results.
2. RTC:
Real Time Clock
3. DECODER:
Decodes the address.
4. ROM/RAM I/F:
Controls the SELECT signal of ROM or RAM and the bank
switching.
switching.
5. CIS I/F:
Controls the document reading.
6. IMAGE DATA RAM:
This memory is programmed into the ASIC and uses 8 KB
for the image processing. (See Fig. A.*)
for the image processing. (See Fig. A.*)
7. THERMAL HEAD I/F:
Transmits the recorded data to the thermal head.
8. MOTOR I/F:
Controls the transmission motor which feeds the document.
Controls the receiving motor which feeds the recording
paper.
paper.
9. OPERATION PANEL I/F:
Serial interface with Operation Panel.
10. I/O PORT:
I/O Port Interface.
11. ANALOG UNIT:
Electronic volume for the handset and the monitor.
Sends beep tones, etc.
8.3.1.2.
ASIC (IC501)
Note*:
This memory is incorporated into the ASIC (IC501) and used for the image processing.
Fig. A shows the memory map of the Image Data RAM.
126
KX-FB423RU-W
8.3.1.4.
DYNAMIC RAM (IC503)
8.3.1.3.
FLASH MEMORY (IC523)
The 512KB ROM (FLASH MEMORY) carries a common area of 32KB and bank areas which each have 8KB (BK4~BK63). The
addresses from 0000H to 7FFFH are for the common area and from 8000H to 9FFFH are for the bank areas.
addresses from 0000H to 7FFFH are for the common area and from 8000H to 9FFFH are for the bank areas.
The DRAM serves as CPU and receives memory.
The address is F200H~F3FFH (DRAM access window 1) and F600H~F7FFH (DRAM access window 2).
Descriptions of Pin Distribution (IC501)
NO.
SIGNAL
I/O
POWER SUPPLIED
VOLTAGE
DESCRIPTION
1
VSSA
GND
POWER SOURCE (ANALOG GND)
2
VDDA 3.3
3.3V
POWER SOURCE (ANALOG +3.3V)
3
AIN1
A
3.3V
CCD IMAGE SIGNAL INPUT
4
AIN2
A
3.3V
THERMISTOR TEMPERATURE WATCH INPUT
5
AIN3
A
3.3V
-----------
6
AMON
A
3.3V
ANALOG SIGNAL MONITOR TERMINAL
7
VSS
GND
POWER SOURCE (GND)
8
X32OUT
O
3.3V/BATT
RTC (32.768KHz) CONNECTION
9
X32IN
I
3.3V/BATT
RTC (32.768KHz) CONNECTION
10
VDD (3.3V / B)
-----
POWER SOURCE (+3.3V/LITHIUM BATTERY)
11
XBACEN
I
3.3V/BATT
BACKUP ENABLE
12
XRAMCS
O
3.3V/BATT
NOT USED
13
VDD (3.3V / B)
-----
POWER SOURCE(+3.3V / LITHIUM BATTERY)
14
VDD (2.5V/B)
-----
POWER SOURCE (+2.5V / LITHIUM BATTERY)
15
FTG
O
3.3V
SH SIGNAL OUTPUT FOR CIS (SI)
16
F1
O
3.3V
01 SIGNAL OUTPUT FOR CIS (CLK)
17
F2/OP
O
3.3V
OUTPUT PORT (HSTXMUTE)
18
FR/OP
O
3.3V
OUTPUT PORT (MDMRST)
19
CPC
I
3.3V
INPUT PORT (PTOP)
20
RVN
I
3.3V
RVN
21
IRDATXD/IOP
O
3.3V
OUTPUT PORT (CISLED)
22
IRDARXD/IOP80
I
3.3V
INPUT PORT (DOCU)
23
TXD/IOP
I
3.3V
INPUT PORT (RDPOS)
24
RXD/IOP
O
3.3V
OUTPUT PORT (SENLED1)
25
XRTS/IOP
I
3.3V
INPUT PORT (HOOK)
26
XCTS/IOP
O
3.3V
OUTPUT PORT (SPMUTE)
27
VDD (2.5V)
-----
POWER SOURCE (+2.5V)
28
TONE1
A
3.3V
TONE OUTPUT
29
TONE2
A
3.3V
TONE OUTPUT
30
VOLUREF
A
3.3V
ANALOG REF VOLTAGE
31
VOLUOUT
A
3.3V
VOLUME OUTPUT
32
VOLUIN
A
3.3V
VOLUME INPUT
33
XNMI
I
3.3V
HIGH FIXED
34
FMEMDO/IOP
O
3.3V
OUTPUT PORT (ON-MREN)
35
VDD (3.3V)
-----
POWER SOURCE (+3.3V)
36
VSS
GND
POWER SOURCE (GND)
37
VSS
GND
POWER SOURCE (GND)
38
VDD (3.3V)
-----
POWER SOURCE (+3.3V)
39
MIDAT/IOP
O
3.3V
OUTPUT PORT (TONE1EN)
40
MICLK/IOP
I
3.3V
INPUT PORT (OP RESET)
41
MILAT/IOP
O
3.3V
OUTPUT PORT (ASFMHLD)
42
20KOSC/IOP
I
3.3V
INPUT PORT (BELL)
43
XWAIT
I
3.3V
INPUT PORT (KOVER)
44
HSTRD/IOP
O
3.3V
NOT USED
45
HSTWR/IOP
O
3.3V
NOT USED
46
XOPRBE
O
3.3V
MFCS
47
ADR15
O
3.3V
CPU ADDRESS BUS 15 (NOT USED)
48
ADR14
O
3.3V
CPU ADDRESS BUS 14 (NOT USED)
49
ADR13
O
3.3V
CPU ADDRESS BUS 13 (NOT USED)
50
VDD (2.5V)
-----
POWER SOURCE (+2.5V)
51
XOUT
O
3.3V
SYSTEM CLOCK (24MHz)
52
XIN
I
3.3V
SYSTEM CLOCK (24MHz)
53
VSS
GND
POWER SOURCE (GND)
54
VDD (3.3V)
-----
POWER SOURCE (+3.3V)
127
KX-FB423RU-W
NO.
SIGNAL
I/O
POWER SUPPLIED
VOLTAGE
DESCRIPTION
55
XTEST
O
3.3V
24MHz CLOCK
56
TEST1
I
3.3V
HIGH FIXED
57
TEST2
I
3.3V
HIGH FIXED
58
TEST3
I
3.3V
HIGH FIXED
59
TEST4
I
3.3V
HIGH FIXED
60
XMDMINT
I
3.3V
MODEM INTERRUPT
61
XMDMCS
O
3.3V
MODEM CHIP SELECT
62
XRAS/IOP
O
3.3V
DRAM (IC503) ROW ADDRESS STROBE
63
XCAS1/IOP
O
3.3V
DRAM (IC503) COLUMN ADDRESS STROBE
64
XCAS2/IOP
O
3.3V
DRAM(IC503) CHIPSELECT
65
XRESCS2
O
3.3V
FLASH CHIP SELECT
66
DB3
I/O
3.3V
CPU DATA BUS 3
67
DB2
I/O
3.3V
CPU DATA BUS 2
68
DB4
I/O
3.3V
CPU DATA BUS 4
69
DB1
I/O
3.3V
CPU DATA BUS 1
70
DB5
I/O
3.3V
CPU DATA BUS 5
71
VDD (3.3V)
-----
POWER SOURCE (+3.3V)
72
VSS
GND
POWER SOURCE (GND)
73
VSS
GND
POWER SOURCE (GND)
74
VDD (3.3V)
-----
POWER SOURCE (+3.3V)
75
DB0
I/O
3.3V
CPU DATA BUS 0
76
DB6
I/O
3.3V
CPU DATA BUS 6
77
DB7
I/O
3.3V
CPU DATA BUS 7
78
XROMCS
O
3.3V
ROM (IC523) CHIP SELECT
79
RD
O
3.3V
CPU RD
80
WR
O
3.3V
CPU WR
81
ADR0
O
3.3V
CPU ADDRESS BUS 0
82
ADR1
O
3.3V
CPU ADDRESS BUS 1
83
ADR2
O
3.3V
CPU ADDRESS BUS 2
84
ADR3
O
3.3V
CPU ADDRESS BUS 3
85
ADR4
O
3.3V
CPU ADDRESS BUS 4
86
ADR5
O
3.3V
CPU ADDRESS BUS 5
87
VSS
GND
POWER SOURCE (GND)
88
VDD (2.5V)
-----
POWER SOURCE (+2.5V)
89
ADR6
O
3.3V
CPU ADDRESS BUS 6
90
ADR7
O
3.3V
CPU ADDRESS BUS 7
91
ADR8
O
3.3V
CPU ADDRESS BUS 8
92
ADR9
O
3.3V
CPU ADDRESS 9
93
ADR10
O
3.3V
CPU ADDRESS 10
94
ADR11
O
3.3V
CPU ADDRESS 11
95
ADR12
O
3.3V
CPU ADDRESS 12
96
RBA0
O
3.3V
ROM/RAM BANK ADDRESS 0
97
RBA1
O
3.3V
ROM/RAM BANK ADDRESS 1
98
RBA2
O
3.3V
ROM/RAM BANK ADDRESS 2
99
RBA3
O
3.3V
ROM/RAM BANK ADDRESS 3
100
RBA4
O
3.3V
ROM/RAM BANK ADDRESS 4
101
RBA5
O
3.3V
ROM/RAM BANK ADDRESS 5
102
RBA6/IOP96
O
3.3V
A19
103
STB1
O
3.3V
STROBE SIGNAL OUTPUT TO THERMAL HEAD
(VIA GATE ARRAY)
(VIA GATE ARRAY)
104
STB2
O
3.3V
STROBE SIGNAL OUTPUT TO THERMAL HEAD
(VIA GATE ARRAY)
(VIA GATE ARRAY)
105
STB3
O
3.3V
NOT USED
106
XRESET
I
3.3V
RESET INPUT
107
VDD (3.3V)
-----
POWER SOURCE (+3.3V)
108
VSS
GND
POWER SOURCE (GND)
109
VSS
GND
POWER SOURCE (GND)
110
VDD (3.3V)
-----
POWER SOURCE (+3.3V)
111
XORESET
O
3.3V
LATED RESET SIGNAL OUTPUT
112
VDD(5V)
-----
POWER SOURCE (+5V)
113
VSS
GND
POWER SOURCE (GND)
114
XRESETI
I
3.3V
RESET INPUT
115
WDERR
O
3.3V
WATCHED ERROR OUTPUT SIGNAL
116
THDAT
O
3.3V
RECORDED IMAGE OUTPUT
117
THCLK
O
3.3V
CLOCK OUTPUT FOR DATA TRANSFER
118
THLAT
O
3.3V
PULSE OUTPUT FOR DATA LATCH
128
KX-FB423RU-W
