Panasonic DMC-F7PP / DMC-F7E / DMC-F7E1 / DMC-F7B / DMC-F7B1 / DMC-F7A / DMC-F7EN Service Manual ▷ View online
A
B
C
D
E
F
G
H
1
2
3
4
5
6
7
8
9
10
11
12
3V
1.4V
1.5V
3V
3V
0V
1.6V
1.6V
3V
0V
0V
3V
3V
0V
3V
3V
3V
3V
0V
3V
3V
0V
3V
0V
2.6V
0.8V
0V
0V
2V
2V
3V
3V
0V
3.2V
3V
3V
0V
0V
0V
0V
0V
2.6V
0V
0V
0V
2.1V
2.1V
5.1V
1.8V
5.1V
0V
0.7V
0V
5.1V
5.2V
1V
3V
3V
1.2V
0.6V
5.2V
JACK CTL
4
V OUT
5
SO1
6
TXD
7
RXD
SCK1
9
PR XDEN
10
PR XSDRQ
K REG
P JUDGE
13
GND
14
GND
GND
GND
15
16
16
CN4
8
11
12
12
4
5
6
1
3
2
CVBS
SV10
SO1
SV1
SCK1
SV2
TXD
SV4
RXD
SV5
PR XSDRQ
SV7
XSDEN
SV6
P JUDGE
SV9
JACK CTL
SV3
K REG
SV8
A
B
B
C
D
E
D
E
F
G
H
H
I
A
B
C
D
E
E
F
G
H
H
I
C104
4V220
R105
68
C103
1
C101
6.3V10
C102
0.01
R102
0
L101
22 uH
IC4501
HD33660A34FP
HD33660A34FP
(SUB
-COM .)
21
GND
20
GND
19
GND
18
GND
17
GND
22
GND
23
GND
27
GND
50
BUZZER+
51
BUZZER-
31
STROB AD
25
SENS EVR
69
35
34
68
35
34
68
67
32
66
32
66
70
V BATT
AREG SO
EVR ADJ
I MTR
BAT DOWN
UNREG
AREG CLK
REG CS
J
J
33
PWR CHECK
1
2
2
AL +3.1V
AL +3.1V
AL +3.1V
CN2
CN2
R LED
SS13
G LED
SS12
IIC SDA
SS1
IIC SCL
SS2
RST CPU
SS3
INT CPU
SS4
STB CPU
SS5
FL RST
SS6
K PLAY
SS7
F COVER
SS8
ST LED
SS9
REG +4.9V
PV1
REG +3.1V
PV3
R4536
0
SUB PB7
3
SUB PB6
4
SUB PB5
5
SUB RES
7
SUB NMI
6
AL +3.1V
1
GND
2
SUB SO
8
SUB SI
9
SUB SCK
10
CN7
R4542
0
R4516
0
X4501
C4506
0.1
R4514
10M
R4535
0
C4503
10P
C4504
9P
4
1
2
3
X4502
(32.768kHz)
R4533
0
R4504
10K
R4503
4700
R4502
150K
R4505
47K
C4501
1
R4507
2700
R4506
10K
D4501
B0ADCC000006
3
4
1
2
Vcc
OUT
NC
GND
R4530
0
R4511
0
R4510
0
R4509
0
R4508
470K
R4512
470K
C4507
0.01
O6
O7
O8
O9
O7
O8
O9
O10
O11
O11
O15
L4501
22 uH
C4510
6.3V22
R4531
0
R4513
10K
C4502
0.01
O5
O12
O13
O13
O14
O16
O17
O18
O19
O20
O21
O22
O23
O24
O18
O19
O20
O21
O22
O23
O24
O14
O24
O17
O2
O21
O18
O20
O23
R4524
270
O13
CN2
R4539
1K
R4527
0
R4525
2200
O16
R4540
1K
R4526
270
O15
R4541
1K
O22
R4529
0
R4528
0
R4538
12K
R4517
12K
R4522
22K
R4523
100K
C4509
0.1
O19
C4508
0.1
O1
USB SEL
SS10
USB ON
SS11
O1
O2
O2
O4
O10
O6
O5
O8
O7
O9
O3
O12
O11
A
B
C
D
E
F
G
R4521
0
C4505
0.1
A
B
C
D
E
G
F
GND
PV4
O3
O4
O4
Q4503
B1GDCFNN0001
B1GDCFNN0001
Q4504
B1GBCFNN0001
B1GBCFNN0001
IC101
C1AB00001160
C1AB00001160
IC4502
PST3427UR
PST3427UR
Q4502
B1GBCFLL0001
B1GBCFLL0001
Q4501
2SC4617-GRTL
2SC4617-GRTL
CHRG EXE
11
O25
REG +17.5V
PV2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
N.C.
A
Vcc
X2
X1
VCL
RES
TEST
Vss
OSC2
OSC1
Vcc
BZ
ENV
N.C.
N.C.
N.C.
PB
K PLAY
F COVER
USB VBUS
STB CPU
RST CPU
INT CPU
IIC SDA
IIC SCL
N.C.
N.C.
P76
USB D+SW
FL RST
N.C.
N.C.
NMI
P80
FTIOB
EVR
ADJ
BZ
FREQ
P87(STMR)
AREG
CLK
SI
AREG
SO
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
PWR CHEK
REG CS
BAT DOWN
STROB AD
M DIAL
BATT CHECK
T BAT
I MTR
V BATT
N.C.
N.C.
P86(RED)
P85(GRN)
CHRG EXE
O25
R4544
0
R106
0
R107
0
MAIN (SUB-u-COM) SCHEMATIC DIAGRAM
DMC-F7PP/E/B/A/EN (SUB-u-COM) SCHEMATIC DIAGRAM
POSITIVE VOLTAGE LINE
TO MAIN (SENSOR)
CIRCUIT (12-C)
TO MAIN (MAIN u-COM)
CIRCUIT (12-B)
TO MAIN (PROCESS 1)
CIRCUIT (8-F)
TO MAIN (PROCESS 1)
CIRCUIT (1-E)
TO LENS DRIVE/STROBE
CIRCUIT (CN102)
TO MAIN (PROCESS 1)
CIRCUIT (9-H)
TO MAIN (MAIN u-COM)
CIRCUIT (12-B,C)
TO REGULATOR CIRCUIT
(CN102)
TO MAIN (SD I/F)
CIRCUIT (12-G)
TO REGULATOR CIRCUIT
(CN102)
TO JACK CIRCUIT
(CN201)
(CN201)
DMC-F7PP / DMC-F7E / DMC-F7E1 / DMC-F7B / DMC-F7B1 / DMC-F7A / DMC-F7EN
21
A
B
C
D
E
F
G
H
1
2
3
4
5
6
7
8
9
10
11
12
3.1
3.1
3.1
3.1
0
(1.2)
0
3.1
(2.6)
3.1
(2.9)
0.8
(1)
0.8
(0.4)
0.4
0.8
(0.5)
0.8
0.8
(1.5)
0.8
(0.3)
0.8
0.8
(1.7)
0
(0.8)
0.8
(1)
0.8 (1)
0.8 (1)
0
0.8 (1.2)
0.8 (1.2)
0.8 (1)
0.5
3.1
3.1
0
0
3.1
0
0
0
0
3.1
3.1
3.1
3.1
0
3.1
3.1
3.1
0
0
3.1
3.1
3.1
3.1
3.1
0
3.1
3.1
3.1
2.8
3.1
0
(0.3)
0
3.1
(1.2)
P30
P32
P31
P27
P28
P29
P7
P6
P5
OE
SI5
WE
SI6
MCLK
SI7
SD DK
SI1
SD IRQ
SI2
SD IRQ2
SI3
SD CS
SI4
SD STBY
SI9
SI0
SI10
SCK0
SI11
SO0
SI12
JVC PLAY
SI13
K CROSS
SI14
BACK OPE
SI15
K ZOOM
SI16
REG+3.1V
PS1
SPI CS
SI17
SPI CD
SI18
MCU RST
SI8
MCU D20
SI31
MCU D19
SI30
MCU D18
SI29
MCU D17
SI28
MCU D16
SI27
MCU D21
SI32
MCU D22
SI33
MCU D23
SI34
MCU D24
SI35
MCU D25
SI36
MCU D26
SI37
MCU D27
SI38
MCU D28
SI39
MCU D29
SI40
MCU D30
SI41
MCU A07
SI26
MCU A06
SI25
MCU A05
SI24
MCU A04
SI23
MCU A03
SI22
MCU A02
SI21
MCU A01
SI20
MCU D31
SI42
DBE CLK
SI43
P26
P25
P24
P16
P17
P18
P19
P20
P1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
N.C.
V
DD
MNA4
MNA3
MNA2
MNA1
MND15
MND14
MND13
MND12
MND1
1
MND10
MND9
MND8
MND7
MND6
MND5
N.C.
N.C.
N.C.
MND4
MND3
Vss
V
DD
MND2
MND1
MND0
XMNDK
MNIRQ
MNIRQ2
N.C.
N.C.
TESTOUT3
TESTOUT2
TESTOUT1
TESTMD1
TESTMD0
TESTOUT0
N.C.
TESTOUT4
SDCLK
SDOCD
V
DD
Vss
SDOCMD
SDOWP
SDODA
T3
SDODA
T2
SDODA
T1
SDODA
T0
V
DD
Vss
SD1CMD
SD1DA
T3
SD1DA
T2
N.C.
N.C.
N.C.
N.C.
N.C.
SD1DAT1
SD1DAT0
SD1CD
SD1WP
TESTMODE
MINTESTY
XSTANDBY
Vss
MCLK
XRST
XMNCS
XMNRE
XMNWE
MNA7
MNA6
MNA5
IC5001
MN5772ZZLD
MN5772ZZLD
(SD CARD I/ F)
R5030
0
R5029
0
C5002
0.1
C5003
0.1
C5004
0.1
R5112
22
R5202
47K
R5105
47K
R5113
22
R5101
47K
R5108
22
R5109
22
R5102
47K
R5115
0
R5104
47K
R5103
47K
R5110
22
R5106
47K
R5114
0
R5205
47K
R5111
22
P1
P2
P3
P4
P5
P6
P7
P8
P9
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P24
P2
P3
P4
P15
P13
P14
P12
P11
P10
P9
P8
P23
P22
P21
R5069
0
R5065
0
R5067
0
R5077
0
R5053
47K
R5054
47K
R5055
47K
33
REG +3.1V
R5107
47K
P34
P35
P40
P33
K ZOOM
32
REG +3.1V
31
K CROSS
30
BACK OPE
29
K REG
28
K PLAY
27
G LED
26
R LED
25
SD0DATA3
24
SD0DATA2
23
SDCLK
22
SD0CMD
21
SD0DAT1
20
SD0DAT0
19
SDOWP
18
SD0CD
17
CN3
A
B
C
D
E
F
G
B
C
D
D
E
F
G
H
P39
P37
P38
K REG
SI19
P42
P36
R LED
SS13
G LED
SS12
H
A
R5059
47K
R5060
47K
R5061
47K
R5062
47K
C5001
0.1
P42
R5079
0
P41
GND
PS2
L5001
0
MAIN (SD I/F) SCHEMATIC DIAGRAM
DMC-F7PP/E/B/A/EN MAIN (SD I/F) SCHEMATIC DIAGRAM
POSITIVE VOLTAGE LINE
TO MAIN (MAIN u-COM)
CIRCUIT (12-A)
TO MAIN (PROCESS 1)
CIRCUIT (9-A,B)
TO MAIN (PROCESS 2)
CIRCUIT (12-H)
TO MAIN (MAIN u-COM)
CIRCUIT (11-D)
TO MAIN (SUB-u-COM)
CIRCUIT (2-B)
CIRCUIT (2-B)
TO MONITOR CIRCUIT
(CN301)
(CN301)
DMC-F7PP / DMC-F7E / DMC-F7E1 / DMC-F7B / DMC-F7B1 / DMC-F7A / DMC-F7EN
22
9.1. IC3001 DBE
Pin
No.
Signal Name
I/O
Description
1
AVSS1
-
GND
2
AVSS3
-
GND
3
AVSS4
-
GND
4
VCLK
I
27MHz Clock input terminal
5
VERT_RESE
T
T
-
Low:fixed
6
ZEB_SKIN
O
TEST port (TL3001)
7
USB_VDD
-
High:fixed (VDD)
8
RESET
I
Reset input terminal
9
SCAN
-
Low:fixed
10
TEST1/
GPI01
(RXD_T)
GPI01
(RXD_T)
I
USB differential amplifier input terminal
11
TEST4/
GPI04
(VPO)
GPI04
(VPO)
O
Differential driver signal output terminal
12
CD2
-
Low:fixed
13
CF_D11
-
High:fixed
14
CF_D13
-
High:fixed
15
CF_D7
-
High:fixed
16
CF_D15
-
High:fixed
17
N.C.
-
Not used
18
N.C.
-
Not used
19
N.C.
-
Not used
20
N.C.
-
Not used
21
N.C.
-
Not used
22
N.C.
-
Not used
23
N.C.
-
Not used
24
CF_WAIT
-
Low:fixed
25
CF_REG
-
Low:fixed
26
CF_D0
-
High:fixed
27
CF_D2
-
High:fixed
28
CF_D10
I
Data input terminal (fixed)
29
MD25
I
Data input terminal (fixed)
30
MD21
I
Data input terminal (fixed)
31
MD19
I/O
Data input/output terminal
32
MD30
I
Data input terminal (fixed)
33
MD16
I/O
Data input/output terminal
34
MA4
O
Address output terminal
35
MA3
O
Address output terminal
36
MA5
O
Address output terminal
37
MA1
O
Address output terminal
38
MA0
O
Address output terminal
39
MA9
O
Address output terminal
40
MA11
O
Address output terminal
41
MCLK_RET
(MCLK_I)
(MCLK_I)
I
Clock input
42
MCS[0]
(MCS)
(MCS)
O
Chip select output terminal
43
BSEL[0]
(Bank
Address 1)
(Bank
Address 1)
O
Bank address output terminal
44
RAS
(Raw
Address
Strobe)
(Raw
Address
Strobe)
O
Bertical address latch trigger
input terminal
(Low:Active)
input terminal
(Low:Active)
45
DQM0
(DQML)
(DQML)
I/O
Input maskable/Output enable
46
MD9
I/O
Data input/output terminal
47
MD5
I/O
Data input/output terminal
48
MD12
I/O
Data input/output terminal
49
MD2
I/O
Data input/output terminal
50
MD15
I/O
Data input/output terminal
51
CPUSEL[1]
-
Low:fixed
Pin
No.
Signal Name
I/O
Description
52
SA0
O
Address output terminal
53
SA2
O
Address output terminal
54
SA5
O
Address output terminal
55
SA8
O
Address output terminal
56
SA12
O
Address output terminal
57
SA15
O
Address output terminal
58
RD
I
Output(read) enable input terminal
59
WRH
I
WRH input terminal
60
CS
I
Chip select input terminal
61
SD14
I/O
Data input/output terminal
62
SD11
I/O
Data input/output terminal
63
SD7
I/O
Data input/output terminal
64
SD4
I/O
Data input/output terminal
65
SD0
I/O
Data input/output terminal
66
AFE_D10
I/O
Data input/output terminal
67
AFE_D6
I/O
Data input/output terminal
68
AFE_D2
I/O
Data input/output terminal
69
AFE_CLK3X
I
Clock input
70
AFE_VPIX
I
VPIX input terminal
71
SER_SDEN
-
High:fixed
72
SER_SD
-
High:fixed
73
COMP+
I
Comparator +signal input terminal
74
Cr+(R)
O
Cr signal output terminal
75
CORE_VSS
-
GND
76
CARRIER_O
-
Low:fixed
77
HSYNC
I
HSYNC input terminal
78
USB_D+
I/O
USB input/output (+) terminal
79
USB_4XCLK
I
48MHz clock input terminal
80
TME
-
Low:fixed
81
TEST2/
GPI02
(VP)
GPI02
(VP)
I
Output gate control signal input
terminal
(with VM)
terminal
(with VM)
82
TEST5/
GPI05
(VMO)
GPI05
(VMO)
O
Differential driver signal output terminal
83
CD1
-
Low:fixed
84
CF_D4
-
High:fixed
85
CF_D6
-
High:fixed
86
N.C.
-
Not used
87
N.C.
-
Not used
88
N.C.
-
Not used
89
N.C.
-
Not used
90
CF_RDY
-
Low:fixed
91
VDD
-
VDD
92
N.C.
-
Not used
93
N.C.
-
Not used
94
N.C.
-
Not used
95
BVD1
-
Low:fixed
96
CF_D9
-
High:fixed
97
N.C.
-
Not used
98
MD22
I
Data input terminal (fixed)
99
MD27
I
Data input terminal (fixed)
100
MD29
I/O
Data input/output terminal
101
MD17
I
Data input terminal (fixed)
102
VSS
-
GND
103
VDD
-
VDD
104
MA2
O
Address output terminal
105
MA7
O
Address output terminal
106
MA8
O
Address output terminal
107
BA1
(Bank
Address 1)
(Bank
Address 1)
O
Bank address output terminal
108
CORE_VSS_
PLL
PLL
-
GND
109
RT_MCLKIN
-
Low:fixed
9 I/O CHART
23
DMC-F7PP / DMC-F7E / DMC-F7E1 / DMC-F7B / DMC-F7B1 / DMC-F7A / DMC-F7EN
Pin
No.
Signal Name
I/O
Description
110
N.C.
-
Not used
111
CAS
(Column
Address
Strobe)
(Column
Address
Strobe)
O
(Low:Active)
112
MD8
I/O
Data input/output terminal
113
MD6
I/O
Data input/output terminal
114
MD11
I/O
Data input/output terminal
115
MD3
I/O
Data input/output terminal
116
MD14
I/O
Data input/output terminal
117
MD0
I/O
Data input/output terminal
118
SA1
O
Address output terminal
119
SA3
O
Address output terminal
120
SA6
O
Address output terminal
121
SA9
O
Address output terminal
122
SA13
O
Address output terminal
123
WAIT
O
WAIT signal output terminal
124
WRL
I
WRL input terminal
125
IRQ
O
Interrupt signal output terminal
126
SD13
I/O
Data input/output terminal
127
SD10
I/O
Data input/output terminal
128
SD6
I/O
Data input/output terminal
129
SD3
I/O
Data input/output terminal
130
AS
I
ASN input terminal
131
AFE_D9
I/O
Data input/output terminal
132
AFE_D5
I/O
Data input/output terminal
133
AFE_D1
I/O
Data input/output terminal
134
AFE_SOF
I
SQF input terminal
135
SER_SCLK
-
High:fixed
136
AVDD
-
VDD power supply
137
AVDD2
-
VDD power supply
138
AVDD3
-
VDD power supply
139
VSS
-
GND
140
VSYNC/
MCKE
MCKE
O
VSYNC/Clock enable output terminal
141
USB_D-
I/O
USB input/output (-) terminal
142
BCLKOUT
O
DBE clock output
143
TESTMODE
_SCAN
_SCAN
-
Low:fixed
144
CORE_VSS
-
GND
145
TEST6/GPI0
6
(USB_OE)
6
(USB_OE)
O
USB output enable output terminal
146
VSS
-
GND
147
CF_D12
-
High:fixed
148
VSS
-
GND
149
N.C.
-
Not used
150
VSS
-
GND
151
VSS
-
GND
152
N.C.
-
Not used
153
CORE_VSS
-
GND
154
VSS
-
GND
155
VSS
-
GND
156
CF_D1
-
High:fixed
157
VSS
-
GND
158
MD24
-
High:fixed
159
VSS
-
GND
160
MD20
I/O
Data input/output terminal
161
VSS
-
GND
162
VSS
-
GND
163
CORE_VSS
-
GND
164
VSS
-
GND
165
VSS
-
GND
166
MA10
O
Address output terminal
167
VSS
-
GND
168
VSS
-
GND
169
AVSS_PLL
-
Low:fixed (GND)
Pin
No.
Signal Name
I/O
Description
170
VSS
-
GND
171
VSS
-
GND
172
CORE_VSS
-
GND
173
VSS
-
GND
174
VSS
-
GND
175
VSS
-
GND
176
CORE_VSS
-
GND
177
SA4
O
Address output terminal
178
VSS
-
GND
179
SA10
O
Address output terminal
180
SA14
O
Address output terminal
181
VSS
-
GND
182
CORE_VSS
-
GND
183
VSS
-
GND
184
SD9
I/O
Data input/output terminal
185
VSS
-
GND
186
SD2
I/O
Data input/output terminal
187
BCLK
I
Clock input
188
AFE_D8
I/O
Data input/output terminal
189
AFE_D4
I/O
Data input/output terminal
190
AFE_D0
I/O
Data input/output terminal
191
VSS
-
GND
192
FS_ADJUST
-
Low:fixed
193
Y+(G)
O
G signal output terminal
194
Cb+(B)
O
Cb signal output terminal
195
CSYNC
O
Composite SYNC output
196
USB_VSS
-
GND
197
TESTMODE
-
Low:fixed
198
TEST0/
GPI00
GPI00
-
High:fixed
199
TEST3/
GPI03 (VM)
GPI03 (VM)
I
Output gate control signal input
terminal (with VP)
terminal (with VP)
200
TEST7/
GPI07
(SUSPND)
GPI07
(SUSPND)
O
USB bus pause control output terminal
201
CF_D3
-
High:fixed
202
CF_D5
-
High:fixed
203
CF_D14
-
High:fixed
204
N.C.
-
Not used
205
CORE_VDD
-
VDD power supply
206
N.C.
-
Not used
207
N.C.
-
Not used
208
BVD2
-
Low:fixed
209
CF_D8
-
High:fixed
210
CF_WP
-
Low:fixed
211
MD23
I
Data input terminal (fixed)
212
MD26
I
Data input terminal (fixed)
213
MD28
I
Data input terminal (fixed)
214
MD18
I/O
Data input/output terminal
215
MD31
I
Data input terminal (fixed)
216
MA6
O
Address output terminal
217
CORE_VDD
-
VDD power supply
218
VDD
-
VDD
219
MCLKOUT
(MCLK_O)
(MCLK_O)
O
Clock output
220
AVDD_PLL
-
High:fixed (VDD)
221
WE (Write
Enable)
Enable)
O
Write enable terminal
222
MD7
I/O
Data input/output terminal
223
MD10
I/O
Data input/output terminal
224
MD4
I/O
Data input/output terminal
225
MD13
I/O
Data input/output terminal
226
MD1
I/O
Data input/output terminal
227
CPUSEL[0]
-
Low:fixed
228
SA7
O
Address output terminal
229
SA11
O
Address output terminal
230
CORE_VDD
-
VDD power supply
24
DMC-F7PP / DMC-F7E / DMC-F7E1 / DMC-F7B / DMC-F7B1 / DMC-F7A / DMC-F7EN
Click on the first or last page to see other DMC-F7PP / DMC-F7E / DMC-F7E1 / DMC-F7B / DMC-F7B1 / DMC-F7A / DMC-F7EN service manuals if exist.