Panasonic CQ-JH4480K Service Manual ▷ View online
4 WIRING CONNECTION
4
HONDA / CQ-JH4480K
5 BLOCK DIAGRAM
5.1. Main/Display Block
5
HONDA / CQ-JH4480K
6.1. Main Block
IC601 : C2CBHG000123
Pin
No.
Signal
Description
I/O
(V)
FM
AM
CD
1
BEEP
BEEP output (3kHz/100ms)
O
0
0
0
2
PW-
STBY2
STBY2
Power supply IC STBY2
output (H: Power supply IC
ON)
output (H: Power supply IC
ON)
O
5.0
5.0
5.1
3
TEL MUTE External TEL MUTE input
(L:TEL MUTE. )
I
5.0
5.0
5.1
4
FIX.SACTI
VE
VE
FIX-EQ soft select detection
signal
signal
I
0
0
0
5
AMP-STBY Power ICSTBY output(H:
Power IC ON)
O
5.0
5.0
5.1
6
Fix-DATA
-
-
-
-
-
7
Fix-CLK
-
-
-
-
-
8
RDS-
CLK(NC)
CLK(NC)
-
-
-
-
-
9
RDS-
DATA(NC)
DATA(NC)
-
-
-
-
-
10
NC
-
-
-
-
-
11
REST
CPU reset input (L: Reset)
I
5.0
5.1
5.1
12
XT1(SUB)
Sub-clock oscillation
terminal 32.768kHz
terminal 32.768kHz
-
2.6
2.6
2.6
13
XT2(SUB)
Sub-clock oscillation
terminal 32.768KHz
terminal 32.768KHz
-
2.1
2.1
2.2
14
GND
(Connecting to GND)
-
0
0
0
15
X2(MAIN)
Main clock oscillation
terminal 12.396875MHz
terminal 12.396875MHz
-
2.4
2.4
2.5
16
X1(MAIN)
Main clock oscillation
terminal 12.396875MHz
terminal 12.396875MHz
-
2.2
2.2
2.3
17
REGOFF
(Connecting to GND)
-
0
0
0
18
REGC
Regulator output stability
capacity connection
capacity connection
-
5.0
5.0
5.1
19
VDD
Positive power supply
-
5.0
5.0
5.1
20
NC
-
-
-
-
-
21
DATA IN
Input for CD-R reading
I
0
0
0
22
DATA
CONT
CONT
Output for CD-R reading
O
0
0
0
23
NC
-
-
-
-
-
24
NC
-
-
-
-
-
25
NC
-
-
-
-
-
26
NC
-
-
-
-
-
27
NC
-
-
-
-
-
28
AMP
MUTE
MUTE
Power IC Mute: All audio
Mute
Mute
O
0
0
0
29
NC
-
-
-
-
-
30
SEC-CLK
External E2PROM clock
output H/L
output H/L
O
0
0
0
31
SEC-CS
External E2PROM chip
select signal
select signal
O
0
0
0
32
SEC-DATA E2PROM data output (H/L)
O
0
0
0
33
SEC-DI
E2PROM data input (H/L)
I
0
0
0
34
NC
-
-
-
-
-
35
NC
-
-
-
-
-
36
LCD DATA LCD driver data output
(H/L)
O
0
0
0
37
LCD CE
LCD driver chip selection
signal
signal
O
0
0
0
38
LCD SCK
LCD driver clock pulse
output
output
O
0
0
0
39
LCD DI
LCD driver data entry (H/L)
I
5.1
5.1
5.2
40
VSS
(Connecting to GND)
-
0
0
0
41
VDD
Positive power supply
-
5.0
5.1
5.2
42
VOL-B
Volume encoder B input
(H/L)
(H/L)
I
5.1
0.5
0.6
43
VOL-A
Volume encoder A input
(H/L)
(H/L)
I
5.1
0.5
0.6
Pin
No.
Signal
Description
I/O
(V)
FM
AM
CD
44
NC
-
-
-
-
-
45
NC
-
-
-
-
-
46
SET-S0
Destination matrix output 0
O
0
0
0
47
SET-S1
Destination matrix output 1
O
0
0
0
48
SET-S2
-
-
-
-
-
49
SET-S3
-
-
-
-
-
50
SET-R0
Destination matrix input 0
I
0
0
0
51
SET-R1
Destination matrix input 1
I
0
0
0
52
SET-R2
Destination matrix input 2
I
0
0
0
53
SET-R3
Destination matrix input 3
I
0
0
0
54
RDS-
MUTE(NC)
MUTE(NC)
-
-
-
-
-
55
ST IND
Radio stereo indicator input
I
5.2
5.2
5.3
56
NC
-
-
-
-
-
57
TU SCL
Tuner packing clock pulse
output (H/L) PLL clock
output (H/L) PLL clock
O
5.0
5.0
5.2
58
VOL SDA
Data output with built-in
tuner packing E-VOL
tuner packing E-VOL
O
0
0
0
59
VOL CLK
Clock with built-in tuner
packing E-VOL
packing E-VOL
O
0
0
0
60
VOL STB
Strobing with built-in tuner
packing E-VOL signal
packing E-VOL signal
O
0
0
0
61
TU DO
Tuner packing SD input
signal (L)
signal (L)
I
5.2
5.2
5.3
62
NC
-
-
-
-
-
63
TU SDA
Tuner packing data I/O
(H/L)
(H/L)
O
5.2
5.2
5.3
64
CD RESET CD reset signal output
(L:CD reset)
O
5.0
5.0
5.1
65
CD CLK
CD deck serial
communications clock pulse
output
communications clock pulse
output
O
5.0
5.0
5.1
66
CD SOM
CD deck serial
communications data input
communications data input
I
5.2
5.2
2.3
67
CD SIM
CD deck serial
communications data output
communications data output
O
5.0
5.0
0
68
SW3
NCD-9 SW3 input (L: Disk)
I
5.2
5.2
0
69
SW1
NCD-9 SW1 input (L: Disk)
I
5.2
5.2
0
70
CD-ON
H: CD deck CPU
communicate
communicate
O
0
0
5.1
71
ILL-PWM
Ilmi dimar output
O
0
0
0
72
LCD-PWM LCD backlight dimmer
output
O
5.0
5.0
5.2
73
GND(Vpp) GND connection
-
0
0
0
74
RE0-IN
Input of voltage of Leo stud
(A/D input)
(A/D input)
I
0
0
0
75
NC
-
-
-
-
-
76
VCONT
Radio packing VCONT
input (A/D input)
input (A/D input)
I
0.8
1.2
1.3
77
GA NET
CONT(NC)
CONT(NC)
-
-
-
-
-
78
RAMJD
Ram judge input
I
0
0
0
79
MP
RDS multipass input (A/D
input)
input)
I
0
0
0
80
NOISE
RDS noise voltage
detection (A/D input)
detection (A/D input)
I
0
0
0
81
SET EQ
(L: Output)
O
0
0
0
82
AVDD
Analog VDD power supply
-
5.1
5.1
5.2
83
AVREF
Reference voltage input for
analog to digital conversion
analog to digital conversion
-
5.3
5.3
5.4
84
AVSS
(Connecting to GND)
-
0
0
0
85
IE-BUS
OUT
OUT
GA-NET data entry
I
0
0
0
86
IE-BUS IN GA-NET data output
O
0
0
0
87
ACC DET
H:ACC ON L:ACC OFF
I
5.3
5.3
5.4
88
ILL DET
Ilmi input (L: Input)
I
5.0
5.0
5.2
89
NC
(Connecting to GND)
I
0
0
0
6 TERMINALS DESCRIPTION
6
HONDA / CQ-JH4480K
Pin
No.
Signal
Description
I/O
(V)
FM
AM
CD
90
NC
(Connecting to GND)
I
0
0
0
91
NC
(Connecting to GND)
I
0
0
0
92
+B DET
H:+B ON L:+B OFF
I
5.3
5.3
5.4
93
CD EJECT H:CD-EJ OFF L:CD-EJ ON
I
5.0
5.0
5.1
94
(SIO)
L: input
O
-
-
-
95
NC
-
-
-
-
-
96
NC
-
-
-
-
-
97
PW-SCK
Power supply IC clock
output (H/L)
output (H/L)
O
0
0
0
98
PW-DATA Power supply IC data
output
O
0
0
0
99
PW-
LATCH
LATCH
Power supply IC data latch
signal output
signal output
O
5.0
5.0
5.1
100 PW-STBY
Power supply IC STBY
output
output
O
5.0
5.0
5.1
6.2. Display Block
IC901 YEAMLC75853
Pin No.
Name
Description
I/O
Volt (V)
1~32
S1~S32
LCD Segment
O
2.7
33~40 S33~S40
No Connection
-
-
41
COM1
LCD Common
O
2.7
42
COM2
LCD Common
O
2.7
43
COM3
LCD Common
O
2.7
44~47 KS1~KS4
Key Data Output
O
5.3
48K,49
KS5,KS6
No Connection
-
-
50~54 K11~K15
Key Data Input
I
0
55
TEST
(Connect to Ground)
-
0
56
VDD
+5V Power Supply
-
5.3
57
VDD1
+5V Power Supply
-
3.5
58
VDD2
+5V Power Supply
-
1.8
59
VSS
(Connect to Ground)
-
0
60
OSC
CR Oscillator
-
3.9
61
DO
LCD Data Output
O
5.2
62
CE
Chip Enable
I
0.3
63
CLK
LCD Clock Input
I
0
64
DI
LCD Data Input
I
0
7
HONDA / CQ-JH4480K