Panasonic CQ-C7402W Service Manual ▷ View online
Pin
No.
Port
Description
(I/O)
(V)
FM
AM
CD
98
S LED
Security LED control
output
output
O
0
0
5
99
PANEL IN
PANEL detect
I
5.2
5.2
5.2
100 EP CS(NC)
No Connection
-
-
-
-
10.2. Display Block
IC900 C2CBJH000095
Pin
No.
Port
Part Name & Description
I/O
(V)
1
A18
FLASH A17
O
1.5
2
A19
FLASH A18
O
1.7
3
A20
FLASH A19
O
1.3
4
NC
No Connection
-
-
5
NC
No Connection
-
-
6
NC
No Connection
-
-
7
A0
LCD driver data or command
distinction
distinction
O
1.3
8
A1
FLASH A0
O
0.3
9
VSS
Ground potential
-
0
10
A2
FLASH A1
O
0.4
11
A3
FLASH A2
O
0.4
12
A4
FLASH A3
O
0.4
13
A5
FLASH A4
O
1.3
14
A6
FLASH A5
O
0.4
15
A7
FLASH A6
O
0
16
A8
FLASH A7
O
1.3
17
A9
FLASH A8
O
0
18
A10
FLASH A9
O
0
19
A11
FLASH A10
O
1.5
20
A12
FLASH A11
O
1.7
21
VCC
Positive
power
supply
terminal
-
3.5
22
A13
FLASH A12
O
1.4
23
A14
FLASH A13
O
1.6
24
A15
FLASH A14
O
1.7
25
SUB SI UP SO
MAIN-u-com communication
data input and external flash
rewritting
data input and external flash
rewritting
-
0.5
26
SUB SO/UP SI
MAIN-u-com communication
data output and external
flash rewritting
data output and external
flash rewritting
O
1.8
27
UP CLK
External flash rewritting
switch
switch
I
3.5
28
NC
No Connection
-
-
29
FLASH RESET
FLASH reset control output
O
3.5
30
KS1
Key scan signal 1 output
I
0
31
NC
No Connection
-
-
32
NC
No Connection
-
-
33
AVCC
Positive power supply for A/D
converter
converter
-
3.5
34
AVRH
A/D converter standard
voltage input
voltage input
-
3.5
35
AVSS/AVRL
A/D converter ground
potential
potential
-
0
36
TH DETECT
Temperature detection input
I
1.3
37
KS2
Key scan signal 2 output
I
0
38
KS3
Key scan signal 3 output
I
0
39
NC
No Connection
-
-
40
VSS
Ground potential
-
0
41
KI5
Key return signal 5 input
I
0
42
KI4
Key return signal 4 input
I
0
43
KI3
Key return signal 3 input
I
0
44
KI2
Key return signal 2 input
I
0
45
NC
FLASH writing program
starter
starter
I
0
46
NC
FLASH writing program
starter
starter
I
3.5
47
MD0
Mode setting terminal
I
3.5
48
MD1
Mode setting terminal
I
3.5
49
MD2
Mode setting terminal
I
0
50
S W U REQ
SUB-u-com wake up request
INT
3.0
51
ROTARY.1
Rotary encoder signal 1(VOL
UP)
UP)
I
2.5
52
ROTARY.2
Rotary encoder signal 2 (VOL
DOWN)
DOWN)
I
2.5
9
CQ-C7402W
Pin
No.
Port
Part Name & Description
I/O
(V)
53
KI1(SOURCE)
Key return signal 1
INT/I
0
54
REMO INT
Remote
control
signal
interference
INT
3.7
55
NC/WP/ACC
No Connection
O
0
56
NC/A21
No Connection
O
0
57
NC/A22
No Connection
O
0
58
FLASH CE
FLASH chip enable
O
3.4
59
LCD CS
LCD driver chip select
O
3.4
60
NC
No Connection
-
-
61
NC
No Connection
-
-
62
REMO 1
Remote control signal
I
3.7
63
NC
No Connection
-
-
64
VLCD CONT
VLCD 16V control
O
3.4
65
M W U REQ
MAIN-u-com wake up request
O
0
66
LED ON
P.LED control output
O
3.4
67
NC
No Connection
-
-
68
NC
No Connection
-
-
69
FLASH OE/ LCD
RD
RD
FLASH output enable and
LCD driver lead strobe
LCD driver lead strobe
O
3.4
70
LCD WR
LCD driver light strobe signal
O
3.4
71
FLASH WE
FLASH light enable signal
O
3.4
72
NC
No Connection
-
-
73
LCD RESET
LCD driver reset control
O
3.4
74
FLASH RY/BY
FLASH ready/busy input
I
3.4
75
/RST
System reset signal input
I
3.5
76
NC
No Connection
-
-
77
X1A
No Connection
-
-
78
X0A
Not used
I
0
79
VSS
Ground
-
0
80
X0
MAIN system clock input
(12.5MHz)
(12.5MHz)
I
1.3
81
X1
MAIN system clock output
(12.5MHz)
(12.5MHz)
O
1.5
82
VCC
Positive power supply
-
3.5
83
D0
FLASH D0/LCD D0
I
0.9
84
D1
FLASH D1/LCD D1
I
0.9
85
D2
FLASH D2/LCD D2
I
1.1
86
D3
FLASH D3/LCD D3
I
0.9
87
D4
FLASH D4/LCD D4
I
1.0
88
D5
FLASH D5/LCD D5
I
1.1
89
D6
FLASH D6/LCD D6
I
1.1
90
D7
FLASH D7/LCD D7
I
0.8
91
D8
FLASH D8
I/O
0.9
92
D9
FLASH D9
I/O
0.9
93
D10
FLASH D10
I/O
0.9
94
D11
FLASH D11
I/O
0.8
95
D12
FLASH D12
I/O
0.8
96
D13
FLASH D13
I/O
0.7
97
D14
FLASH D14
I/O
0.7
98
D15
FLASH D15
I/O
0.7
99
A16
FLASH A15
O
3.0
100 A17
FLASH A16
O
1.7
10.3. CD Servo Block
IC401 : YESAM275
Pin
No.
Port
Descriptions
I/O
(V)
1
CVSS1
GND
-
0
2
A22
TP407
-
0
3
CVSS2
GND
-
0
4
DVDD1
I/O system (3.3V) power supply
-
3.1
5
A10
Address bus of FLASH ROM
O
3.1
6
-
-
-
-
7
A11
Address bus of FLASH ROM
O
0
8
A12
O
3.1
9
A13
O
3.1
10
A14
O
3.1
11
A15
O
0
12
/CVDD1
CORE CPU system (1.6V) power
supply
supply
-
1.6
13
-
-
-
-
14
DVSS1
GND
-
0
15
CVSS3
GND
-
0
16
/CVDD2
I/O system (3.3V) power supply
-
1.6
17
-
-
-
-
18
-
-
-
-
19
READY
-
-
3.1
20
/PS
FLASH ROM selection signal
O
3.1
21
-
-
-
-
22
-
-
-
-
23
R/W
Lead/light signal to FLASH ROM
O
3.1
24
/MSTRB
Memory access signal
O
3.1
25
-
-
-
-
26
/MSC
-
-
3.1
27
MUTE
Mute signal output (H:Mute on)
O
0
28
-
-
-
-
29
-
-
-
-
30
/HOLD
-
-
3.1
31
BIO
SUBO input
I
0
32
MP/MC
Operation mode setting (external pull-
up)
up)
I
3.1
33
DVDD2
I/O system (3.3V) power supply
-
3.1
34
CVSS4
GND
-
0
35
BD R1
GND
I
0
36
-
-
-
-
37
CVSS5
GND
-
0
38
-
-
-
-
39
-
-
-
-
40
DVSS2
GND
-
0
41
CLK C M AUDIO bit clock input
I
1.6
42
SCK
Clock input
I
3.0
43
LRCK
C
M
AUDIO L/R identifying signal input
I
1.6
44
CDFS
Serial frame sink signal input
I
2.4
45
DATA
CM
CM
AUDIO serial data input
I
1.6
46
-
-
-
-
47
SI
Serial data input
I
0
48
CLK M C AUDIO bit clock output
O
1.6
49
SCK
Clock input
I
3.0
50
CVSS6
GND
-
0
51
-
-
-
-
52
CVDD3
CORE CPU system (1.6V) power
supply
supply
-
1.6
53
LRCK
M
C
AUDIO L/R identifying signal output
O
1.5
54
CDFS
Serial frame sink signal input
I
2.4
55
-
-
-
-
56
DVDD3
I/O system (3.3V) power supply
-
3.1
57
DVSS3
GND
-
0
58
REST
SW
SW
Mechanics deck REST SW input
I
3.1
10
CQ-C7402W
Pin
No.
Port
Descriptions
I/O
(V)
59
DATA
M
C
AUDIO serial data output
O
1.6
60
SO
Serial data output
O
1.1
61
-
-
-
-
62
-
-
-
-
63
/NMI
-
-
3.1
64
/INT0
-
-
3.1
65
/INT1
-
-
3.1
66
BLKCK
Subcode block clock pulse input
I
0
67
/INT3
-
-
3.1
68
CV DD4
CORE CPU system (1.6V) power
supply
supply
-
1.6
69
SW1
Mechanics deck SW1 input
I
0
70
CVSS7
GND
-
0
71
MCLK
Clock output (To Servo DSP)
O
3.1
72
DVSS4
GND
-
0
73
MLD
Command load signal output (To
Servo DSP)
Servo DSP)
I
3.1
74
MDATA
Command data output (To Servo
DSP)
DSP)
O
3.1
75
DVDD4
I/O system (3.3V) power supply
-
3.1
76
DVSS5
GND
-
0
77
CLK MD1 Clock mode setting (L fixation)
I
0
78
CLK MD2 Clock mode setting (H fixation)
I
3.1
79
CLK MD3 Clock mode setting (L fixation)
I
0
80
-
-
-
-
81
SW2
Mechanics deck SW2 input
I
0.2
82
-
-
-
-
83
EMU0
-
-
3.1
84
EMU/OF
F
F
-
-
3.1
85
TDO
-
-
0
86
TDI
-
-
3.1
87
/TRST
-
-
0
88
TCK
-
-
3.1
89
TMS
-
-
3.1
90
CVSS8
GND
-
0
91
CVDD5
CORE CPU system (1.6V) power
supply
supply
-
1.6
92
HPIENA
GND
I
0
93
DVSS6
GND
-
0
94
-
-
-
-
95
CLKENA Oscillation output Cainabl signal
O
0
96
X1
Crystal Connection
O
0.7
97
X2/CLKIN Crystal Connection
I
1.0
98
RS
Reset signal input
I
3.1
99
D0
Data base of FLASH ROM
I/O
0
100
D1
I/O
0
101
D2
I/O
0
102
D3
I/O
0
103
D4
I/O
0
104
D5
I/O
0
105
A16
Address bus of FLASH ROM
O
3.1
106
DVSS7
GND
-
0
107
A17
Address bus of FLASH ROM
O
3.1
108
A18
Address bus of FLASH ROM
O
0
109
A19
TP419
O
0
110
A20
TP416
O
0
111
CVSS9
GND
-
0
112
DVDD5
I/O system (3.3V) power supply
-
3.1
113
D6
Data bus of FLASH ROM
I/O
0
114
D7
I/O
0
115
D8
I/O
0
116
D9
I/O
0
117
D10
I/O
0
118
D11
Data bus of FLASH ROM
I/O
0
119
D12
I/O
0
Pin
No.
Port
Descriptions
I/O
(V)
120
STAT
Status signal input
I
3.0
121
D13
Data path of FLASH ROM
I/O
3.1
122
D14
I/O
0
123
D15
I/O
0
124
-
-
-
-
125
CVDD6
CORE CPU system (1.6V) power
supply
supply
-
1.6
126
CVSS10
GND
-
0
127
-
-
-
-
128
DVSS8
I/O system (3.3V) power supply
-
0
129
-
-
-
-
130
DVDD6
I/O system (3.3V) power supply
-
3.1
131
A0
Address bus of FLASH ROM
O
3.1
132
A1
O
0
133
A2
O
0
134
A3
O
0
135
/RST
Reset signal output(To Servo DSP)
O
3.1
136
A4
Address bus of FLASH ROM
O
0
137
A5
O
3.1
138
A6
O
3.1
139
A7
O
0
140
A8
O
3.1
141
A9
O
3.1
142
CVDD7
CORE CPU system (1.6V) power
supply
supply
-
1.6
143
A12
TP406
-
0
144
DVSS9
GND
-
0
11
CQ-C7402W
11.1. Main Block
IC201 : C1BB00000796
IC241 : C1BB00001047
IC251 : C1BB00001046
11 IC BLOCK DIAGRAM
12
CQ-C7402W
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