Panasonic SV-MP730VGK / SV-MP730VGC / SV-MP730VGH / SV-MP730VGN Service Manual ▷ View online
13 Block Diagram
Overall Block Diagram
FM Audio
Signal
FM Signal
Rec Signal
IC 1 FM Tuner
IC3 DSP
MP3 Decoder
FM Demodulator
IC Recoder
FM Signal
IC2 Flash memory
12MHz Clock
USB port
Control
Control
Headphone
IC4 EL Drive
MIC
DC-DC Conv.
IC 7, 8
AC Adaptor
Battery
LCD Display
13MHz Clock
Rec Signal
IC10
REGULATOR
IC9
REGULATOR
IC301
D-sound
17
SV-MP730VGK / SV-MP730VGC / SV-MP730VGH / SV-MP730VGN
TUNER BLOCK
A
IC1
15
14
14
5
7
9
11
13
12
10
8
6
3
4
4
1
2
2
17
16
19
18
21
20
20
23
22
22
24
CN6
MIC
2.8V
(TO MAIN CIRCUIT CN2)
HEADPHONE
SV-MP730V BLOCK DIAGRAM
TP48
TP47
S.S.G
F=87.5MHz
Mod=30%
Mod f=400Hz
F=87.5MHz
Mod=30%
Mod f=400Hz
233.0mV P-P
REC Signal Line.
Radio (analog) Signal Line.
Notes :
MP3 and FM and IC REC Signal Line.
FM RF Signal Line.
FM RF Signal Line.
Voltage from negative terminal of battery.
( )...MP3 position,[ ]...FM position.
No mark...MP3 and FM position.
( )...MP3 position,[ ]...FM position.
No mark...MP3 and FM position.
C1BB00000997
FM TUNER
FM TUNER
15
14
5
7
9
11
13
12
8
6
3
4
2
17
16
19
18
23
22
24
28
29
26
27
25
38
39
36
37
34
35
32
33
W/R
L GAIN
AGND
V CCD
RFI 1
RF GND
RFI 2
TAGC
CP
OUT
VCO
TANK1
VCO
TANK2
VCC (VCO)
DGND
VCCD
DA
TA
CLOCK
BUSENABLE
BUSMODE
SWPORT1
SWPORT1
XTAL1
XTAL2
LIMDEC1
LIMDEC2
TIFC
V
ref
MPXO
TMUTE
V
AFR
V
AFL
PILFIL
PHASEFIL
GAIN
STABILIZTION
RESONANCE
AMPLIFIER
AMPLIFIER
LIMITER
DEMODULATOR
POWER
SUPPLY
SUPPLY
SOFT
MUTE
MUTE
MPX
DECODER
CRYSTAL
OSCILLATOR
OSCILLATOR
SOFTWARE
PROGRAMMABLE
PROGRAMMABLE
PROT
I/O-MIXER
1st FM
1st FM
AGC
N1
2
TUNING SYSTEM
VCO
IF CENTER
FREQUENCY
ADJUST
LEVEL
ADC
ADC
IF
COUNTER
COUNTER
MUX
Programmable
divider output
divider output
reference frequency
divider output
divider output
I C-BUS
AND
3-WIRE BUS
AND
3-WIRE BUS
2
momo
pilot
SDS
X1
13MHz
IC8
Regulate
Voltage
Voltage
L1
LOOP SW
FM RF Signal Line
1
2
3
4
VIN
VOUT
CE
VSS
IC6
[0] (0)
[2.8]
(0)
(0)
[3.25]
(1.35)
1
2
3
4
VIN
VOUT
CE
VSS
[3.26]
(1.36)
(1.36)
[0]
(0)
(0)
[2.82]
(1.36)
(1.36)
[3.26]
(1.36)
(1.36)
IC6
Regulate
Voltage
Voltage
IC8
[3]
(0)
(0)
18
SV-MP730VGK / SV-MP730VGC / SV-MP730VGH / SV-MP730VGN
9
7
6
8
13
12
17
16
19
18
42
44
43
41
36
37
32
30
31
29
N.C R/B
RE
CE
Vcc Vss
CLE ALE WE WP
I/O
0
0
I/O
1
1
I/O
2
2
I/O
3
3
Vss
Vcc
I/O
4
4
I/O
5
5
I/O
6
6
I/O
7
7
IC2
FLASH MEMORY
15
14
5
7
9
11
13
12
10
8
6
3
4
1
2
17
16
19
18
21
20
23
22
24
CN5
30
28
29
26
27
25
MEMORY BLOCK
B
(TO MAIN CIRCUIT CN1)
D9
KEY
I/O 0 ~ I/O7:
DATA INPUTS/OUTPUTS
The I/O pins are used to input
command,address and data, and
to output data during read operations.
DATA INPUTS/OUTPUTS
The I/O pins are used to input
command,address and data, and
to output data during read operations.
The I/O pins float to high-z when the
chip is deselected or when the
outputs are disabled.
chip is deselected or when the
outputs are disabled.
Vcc:
POWER
Vcc is the power supply for device.
Vss: GROUND
POWER
Vcc is the power supply for device.
Vss: GROUND
R/B: READY/BUSY OUTPUT
The R/B output indicates the status of the device operation.When low, it indicates that a program, erase or random read operation is in process and returns to high
state upon completion.It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.
RE: READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments
the internal column address counter by one.
CE: CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program
or erase opertion. Regarding CE control during read operation, refer to "Page read" section of Device operation.
The R/B output indicates the status of the device operation.When low, it indicates that a program, erase or random read operation is in process and returns to high
state upon completion.It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.
RE: READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments
the internal column address counter by one.
CE: CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program
or erase opertion. Regarding CE control during read operation, refer to "Page read" section of Device operation.
CLE: COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through
the I/O ports on the rising edge of the WE signal.
The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through
the I/O ports on the rising edge of the WE signal.
ALE: ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers.Addresses are latched on the rising edge of WE with ALE high.
WE: WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
The ALE input controls the activating path for address to the internal address registers.Addresses are latched on the rising edge of WE with ALE high.
WE: WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
WP: WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.
PIN DESCRIPTION
PIN DESCRIPTION
Chargeable Control Pin
5V
Q2
Q3
B1ADMD000012
2SA1774STL
CHARGEABLE
CHARGEABLE
0.68
1.04
0.68
0.69
0.69
1.05
D3
MA3J14700L
Battery
SV-MP730V BLOCK DIAGRAM
19
SV-MP730VGK / SV-MP730VGC / SV-MP730VGH / SV-MP730VGN
SV-MP730V BLOCK DIAGRAM
MAIN BLOCK
C
M17
R18
M16
V10
A17
C9
E18
D16 MPMC address 3
MPMC
address 16
MPMC data input/output 0
MPMC data input/output 4
MPMC data input/output 3
MPMC data input/output 2
MPMC data input/output 1
MPMC data input/output 5
MPMC data input/output 7
MPMC data input/output 6
DAI Serial data input
MPMC_NOE:
Output enable for static memories.
Active LOW. Used for static
memory devices.
Output enable for static memories.
Active LOW. Used for static
memory devices.
MPMC_NSTCS_0:
Static memory chip select 0.
Default active LOW. Used
for static memory device.
Static memory chip select 0.
Default active LOW. Used
for static memory device.
U17
U14 T17
T15
B14
A13
A14
A1 A2
A3
B2
A4 B4 A5 B5
DAO Bitclock
DAO Serial data out
DAO W
ordselect
G18 F18 F17
G16
IC3
C2HBZG000008
O
P
Q
R
S
U
V
W
DSP IC
15
14
14
5
7
9
11
13
12
10
8
6
3
4
4
1
2
2
17
16
16
19
18
18
21
20
20
23
22
22
24
CN2
20
2
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
18
19
24
21
22
23
22
23
CN1
25
26
27
28
29
30
26
27
28
29
30
O
P
Q
R
S
S
T
U
V
W
U
V
W
T
A12 MPMC_BLOUT0:
The signals nMPMCBLSOUT[0]
select byte lane [7:0] on the data bus.
Used for static memories.
select byte lane [7:0] on the data bus.
Used for static memories.
3.3V
LCD1 Display
XATLL_OUT
XTALH_IN
HP_OUTCA: HEADPHONE common output reference
HP_OUTCB: HEADPHONE common output reference
ADC_VINR: SADC Right Analog Input
ADC_VINL: SADC Left Analog Input
LCD_RW-WR:
6800 read/write select 8080 active "high" write enable
LCD_E_RD: 6800 enable
8080 active "high" write enable
LCD_DB_4
LCD_DB_5
LCD_DB-7
LCD_DB_6
LCD_DB_1
LCD_DB-3
LCD_DB_2
LCD_RS: 'high' Data
register selsct 'low'
Instruction register select
register selsct 'low'
Instruction register select
LCD_DB-0
LCD_CSB: Chip Select
T1
T4
N1
N2
T10
V9
F3
C2
B3
C1 C3 D2 D1 D3 E2 E3 F2 G2
R3
X2
12MHz
15
3.3V
VDD
IC7
DC-DC
CONV
CONV
IC4
EL
DRIVER
DRIVER
D18
ADC_MIC: Microphone Input
BATTERY
1.2V
J17
USB_DP: Positive USB data line
usb 2.0 FS
usb 2.0 FS
USB_DM:
Negative USB data line
usb 2.0 FS
Negative USB data line
usb 2.0 FS
USB_RPU: Soft connect output usb 2.0 FS
USB_VBUS:
USB Supply detection line
usb 2.0 FS & usb 2.0
USB Supply detection line
usb 2.0 FS & usb 2.0
USB PORT
CN3
3.3V
(TO TUNER CIRCUIT CN6)
(TO MEMORY CIRCUIT CN5)
ICP1
REC Signal Line.
Radio Signal Line.
Notes :
MP3/FM/IC REC Signal Line.
N17
T18
P17
L10
L7
ADAPTOR
IN VCC 5V
IN VCC 5V
DC_DC_LX2:
Connection to DC/DC2 external coil
Connection to DC/DC2 external coil
DC_DC_LX1:
Connection to DC/DC1 external coil
Connection to DC/DC1 external coil
DC_DC_VBAT:
Battery supply voltage
Battery supply voltage
MPMC address 2
MPMC
address 15
MPMC address 5
D18
MPMC address 4
12 MHz clock input
12 MHz clock input
3V
3.26V
3.26V
0V
430.0mV P-P
ICP2
1.2V
DC_DC_VUSB:USB supply voltage
MPMC
address 18
IC9
Battery 1.2V
Battery Chargeable Control Pin
Reset
Chargeable
Control
Control
Q7
Battery
IC10
Regulator
DC/DC1 3.3V output voltage
DC/DC1 3.3V input voltage
Analog supply 10-bit ADC
L35
MPMC data input/output 7
C6
Clear to send
(active low)
K2
256 fs clock input
F16
BCK
LRCK
DIN
SERIAL
INTER-
FACE
INTER-
FACE
DIGITAL
8FS FLUENCY
INTERPOLATOR
with
FUNCTION
CONTROLLER
CONTROLLER
&
PWM
MODU-
LATOR
LATOR
ANALOG
DRIVER
DRIVER
OUTL
OUTR
FUNCTION
CONTROL
INTERFACE
CONTROL
INTERFACE
MC
MD
ML
PDB
SCK
RSTB
DVDD
DGND
POWER SUPPLY
+3.3V
+3.3V +3.3V
A
VDDL
AGND
A
VDDR
IC3
D-SOUND
Serial datd IIC Slave
20
SV-MP730VGK / SV-MP730VGC / SV-MP730VGH / SV-MP730VGN
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